From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id D5C42A046B for ; Tue, 25 Jun 2019 11:06:20 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A821E1BBD9; Tue, 25 Jun 2019 11:06:20 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 00ED01BBD3 for ; Tue, 25 Jun 2019 11:06:18 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jun 2019 02:06:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,415,1557212400"; d="scan'208";a="152235478" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga007.jf.intel.com with ESMTP; 25 Jun 2019 02:06:17 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Jun 2019 02:06:17 -0700 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Jun 2019 02:06:17 -0700 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.72]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.156]) with mapi id 14.03.0439.000; Tue, 25 Jun 2019 17:06:15 +0800 From: "Pei, Andy" To: "Xu, Rosen" , "dev@dpdk.org" CC: "Zhang, Roy Fan" , "Zhang, Qi Z" , "Wu, Jingjing" , "Xing, Beilei" , "Yigit, Ferruh" , "Ye, Xiaolong" Thread-Topic: [PATCH] net/i40e: i40e rework for ipn3ke Thread-Index: AQHVEUjJ1L1jCoz7ekeOapBGuuSOYqZ5dm0AgBsOR/CAAVVU4IAWbcOg Date: Tue, 25 Jun 2019 09:06:14 +0000 Message-ID: <5941F446C088714A85408FA3132CFCBB01037A8F@SHSMSX105.ccr.corp.intel.com> References: <1558602875-429451-1-git-send-email-andy.pei@intel.com> <0E78D399C70DA940A335608C6ED296D73A7781F5@SHSMSX104.ccr.corp.intel.com> <5941F446C088714A85408FA3132CFCBB010283EB@SHSMSX105.ccr.corp.intel.com> <0E78D399C70DA940A335608C6ED296D73A7DE0FE@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <0E78D399C70DA940A335608C6ED296D73A7DE0FE@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: i40e rework for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" + Ye Xiaolong -----Original Message----- From: Xu, Rosen=20 Sent: Tuesday, June 11, 2019 10:35 AM To: Pei, Andy ; dev@dpdk.org Cc: Zhang, Roy Fan ; Zhang, Qi Z ; Wu, Jingjing ; Xing, Beilei ; Yigit, Ferruh Subject: RE: [PATCH] net/i40e: i40e rework for ipn3ke Hi Andy, > -----Original Message----- > From: Pei, Andy > Sent: Monday, June 10, 2019 14:15 > To: Xu, Rosen ; dev@dpdk.org > Cc: Zhang, Roy Fan ; Zhang, Qi Z=20 > ; Wu, Jingjing ; Xing,=20 > Beilei ; Yigit, Ferruh > Subject: RE: [PATCH] net/i40e: i40e rework for ipn3ke >=20 > Hi, Rosen >=20 >=20 > Your ACK is needed if there is no other issue except the CC list >=20 >=20 > -----Original Message----- > From: Xu, Rosen > Sent: Friday, May 24, 2019 9:05 AM > To: Pei, Andy ; dev@dpdk.org > Cc: Zhang, Roy Fan ; Zhang, Qi Z=20 > ; Wu, Jingjing ; Xing,=20 > Beilei ; Yigit, Ferruh > Subject: RE: [PATCH] net/i40e: i40e rework for ipn3ke >=20 > Hi, >=20 > > -----Original Message----- > > From: Pei, Andy > > Sent: Thursday, May 23, 2019 17:15 > > To: dev@dpdk.org > > Cc: Pei, Andy ; Zhang, Roy Fan=20 > > ; Zhang, Qi Z ; Wu,=20 > > Jingjing ; Xing, Beilei=20 > > ; Yigit, Ferruh ; Xu,=20 > > Rosen > > Subject: [PATCH] net/i40e: i40e rework for ipn3ke >=20 > > Add switch_mode argument for i40e PF to specify the specific FPGA=20 > > that i40e PF is connected to. > > i40e PF get link status update via the connected FPGA. > > > > Fixes: c60869e2b742 ("net/i40e: fix link status update") > > Cc: roy.fan.zhang@intel.com > > Cc: qi.z.zhang@intel.com > > Cc: jingjing.wu@intel.com > > Cc: beilei.xing@intel.com > > Cc: ferruh.yigit@intel.com > > Cc: rosen.xu@intel.com >=20 > My understanding cc people should add in git send-email not in patch. >=20 > > Signed-off-by: Andy Pei > > --- > > drivers/net/i40e/i40e_ethdev.c | 128 > > +++++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 122 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/net/i40e/i40e_ethdev.c=20 > > b/drivers/net/i40e/i40e_ethdev.c index cab440f..9873ea0 100644 > > --- a/drivers/net/i40e/i40e_ethdev.c > > +++ b/drivers/net/i40e/i40e_ethdev.c > > @@ -39,11 +39,12 @@ > > #include "i40e_regs.h" > > #include "rte_pmd_i40e.h" > > > > -#define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" > > -#define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" > > -#define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" > > -#define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" > > -#define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" > > +#define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb" > > +#define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list" > > +#define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver" > > +#define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf" > > +#define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec" > > +#define ETH_I40E_SWITCH_MODE_ARG "switch_mode" > > > > #define I40E_CLEAR_PXE_WAIT_MS 200 > > > > @@ -410,6 +411,7 @@ static int i40e_sw_tunnel_filter_insert(struct > > i40e_pf *pf, > > ETH_I40E_SUPPORT_MULTI_DRIVER, > > ETH_I40E_QUEUE_NUM_PER_VF_ARG, > > ETH_I40E_USE_LATEST_VEC, > > + ETH_I40E_SWITCH_MODE_ARG, > > NULL}; > > > > static const struct rte_pci_id pci_id_i40e_map[] =3D { @@ -2784,6 > > +2786,80 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw=20 > > +*hw) > > } > > } > > > > +static int > > +i40e_pf_parse_switch_mode(const char *key __rte_unused, > > + const char *value, void *extra_args) { > > + if (!value || !extra_args) > > + return -EINVAL; > > + > > + *(char **)extra_args =3D strdup(value); > > + > > + if (!*(char **)extra_args) > > + return -ENOMEM; > > + > > + return 0; > > +} > > + > > +static void > > +i40e_pf_switch_mode_link_update(const char *cfg_str, > > + struct rte_eth_dev **switch_ethdev) { > > + char switch_name[RTE_ETH_NAME_MAX_LEN] =3D {0}; > > + char port_name[RTE_ETH_NAME_MAX_LEN] =3D {0}; > > + char switch_ethdev_name[RTE_ETH_NAME_MAX_LEN] =3D {0}; > > + uint16_t port_id; > > + const char *p_src; > > + char *p_dst; > > + int ret =3D -1; > > + > > + /* An example of cfg_str is "IPN3KE_0@b3:00.0_0" */ > > + if (!strncmp(cfg_str, "IPN3KE", strlen("IPN3KE"))) { > > + p_src =3D cfg_str; > > + PMD_DRV_LOG(DEBUG, "cfg_str is %s", cfg_str); > > + > > + /* move over "IPN3KE" */ > > + while ((*p_src !=3D '_') && (*p_src)) > > + p_src++; > > + > > + /* move over the first underline */ > > + p_src++; > > + > > + p_dst =3D switch_name; > > + while ((*p_src !=3D '_') && (*p_src)) { > > + if (*p_src =3D=3D '@') { > > + *p_dst++ =3D '|'; > > + p_src++; > > + } else > > + *p_dst++ =3D *p_src++; > > + } > > + *p_dst =3D 0; > > + PMD_DRV_LOG(DEBUG, "switch_name is %s", switch_name); > > + > > + /* move over the second underline */ > > + p_src++; > > + > > + p_dst =3D port_name; > > + while (*p_src) > > + *p_dst++ =3D *p_src++; > > + *p_dst =3D 0; > > + PMD_DRV_LOG(DEBUG, "port_name is %s", port_name); > > + > > + snprintf(switch_ethdev_name, sizeof(switch_ethdev_name), > > + "net_%s_representor_%s", switch_name, > > port_name); > > + PMD_DRV_LOG(DEBUG, "switch_ethdev_name is %s", > > + switch_ethdev_name); > > + > > + ret =3D rte_eth_dev_get_port_by_name(switch_ethdev_name, > > + &port_id); > > + if (ret) > > + *switch_ethdev =3D NULL; > > + else > > + *switch_ethdev =3D &rte_eth_devices[port_id]; > > + } else > > + *switch_ethdev =3D NULL; > > +} > > + > > int > > i40e_dev_link_update(struct rte_eth_dev *dev, > > int wait_to_complete) > > @@ -2792,6 +2868,11 @@ void i40e_flex_payload_reg_set_default(struct > > i40e_hw *hw) > > struct rte_eth_link link; > > bool enable_lse =3D dev->data->dev_conf.intr_conf.lsc ? true : false; > > int ret; > > + struct rte_devargs *devargs; > > + struct rte_kvargs *kvlist =3D NULL; > > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > > + struct rte_eth_dev *switch_ethdev; > > + char *switch_cfg_str =3D NULL; > > > > memset(&link, 0, sizeof(link)); > > > > @@ -2805,6 +2886,40 @@ void i40e_flex_payload_reg_set_default(struct > > i40e_hw *hw) > > else > > update_link_aq(hw, &link, enable_lse, wait_to_complete); > > > > + devargs =3D pci_dev->device.devargs; > > + if (devargs) { > > + kvlist =3D rte_kvargs_parse(devargs->args, valid_keys); > > + if (kvlist !=3D NULL) { > > + if (rte_kvargs_count(kvlist, > > ETH_I40E_SWITCH_MODE_ARG) > > + =3D=3D 1) { > > + if (!rte_kvargs_process(kvlist, > > + ETH_I40E_SWITCH_MODE_ARG, > > + &i40e_pf_parse_switch_mode, > > + &switch_cfg_str)) { > > + > > + i40e_pf_switch_mode_link_update( > > + switch_cfg_str, > > + &switch_ethdev); > > + > > + if (switch_ethdev) { > > + rte_eth_linkstatus_get( > > + switch_ethdev, > > + &link); > > + } else { > > + link.link_duplex =3D > > + > > ETH_LINK_FULL_DUPLEX; > > + link.link_autoneg =3D > > + > > ETH_LINK_SPEED_FIXED; > > + link.link_speed =3D > > + > > ETH_SPEED_NUM_25G; > > + link.link_status =3D 0; > > + } > > + } > > + } > > + rte_kvargs_free(kvlist); > > + } > > + } > > + > > ret =3D rte_eth_linkstatus_set(dev, &link); > > i40e_notify_all_vfs_link_status(dev); > > > > @@ -12790,4 +12905,5 @@ struct i40e_customized_pctype* > > ETH_I40E_FLOATING_VEB_LIST_ARG "=3D" > > ETH_I40E_QUEUE_NUM_PER_VF_ARG > "=3D1|2|4|8|16" > > ETH_I40E_SUPPORT_MULTI_DRIVER "=3D1" > > - ETH_I40E_USE_LATEST_VEC "=3D0|1"); > > + ETH_I40E_USE_LATEST_VEC "=3D0|1" > > + ETH_I40E_SWITCH_MODE_ARG "=3DIPN3KE"); > > -- > > 1.8.3.1 Acked-by: Rosen Xu