From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DD95A2EFC for ; Fri, 20 Sep 2019 02:58:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 01AB41F1E1; Fri, 20 Sep 2019 02:58:34 +0200 (CEST) Received: from mail1.windriver.com (mail1.windriver.com [147.11.146.13]) by dpdk.org (Postfix) with ESMTP id 0AB121F1AA for ; Fri, 20 Sep 2019 02:58:31 +0200 (CEST) Received: from ALA-HCB.corp.ad.wrs.com ([147.11.189.41]) by mail1.windriver.com (8.15.2/8.15.1) with ESMTPS id x8K0wUwQ015274 (version=TLSv1 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 19 Sep 2019 17:58:30 -0700 (PDT) Received: from ALA-MBD.corp.ad.wrs.com ([169.254.3.87]) by ALA-HCB.corp.ad.wrs.com ([147.11.189.41]) with mapi id 14.03.0468.000; Thu, 19 Sep 2019 17:58:18 -0700 From: "Liu, Yongxin" To: "Liu, Yongxin" , "dev@dpdk.org" CC: "david.w.su@intel.com" , "stephen@networkplumber.org" , "ferruh.yigit@intel.com" , "anuj.mittal@intel.com" , "Hao, Kexin" , "Yang, Liezhi" Thread-Topic: [dpdk-dev] [RFC] igb_uio: change ISR to be threaded when using with RT kernel Thread-Index: AQHVb01+J9aW68BZf0uAR6QP31C1V6czvHgw Date: Fri, 20 Sep 2019 00:58:17 +0000 Message-ID: <597B109EC20B76429F71A8A97770610D19E0837D@ALA-MBD.corp.ad.wrs.com> References: <20190920004525.18259-1-yongxin.liu@windriver.com> In-Reply-To: <20190920004525.18259-1-yongxin.liu@windriver.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [128.224.162.171] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [RFC] igb_uio: change ISR to be threaded when using with RT kernel X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi DPDK experts, This patch is especially used for PREEMPT_RT kernel. Whether it is correct, please share your opinion. Thanks, Yongxin > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Yongxin Liu > Sent: Friday, September 20, 2019 08:45 > To: dev@dpdk.org > Cc: david.w.su@intel.com; stephen@networkplumber.org; > ferruh.yigit@intel.com; anuj.mittal@intel.com; Hao, Kexin; Yang, Liezhi > Subject: [dpdk-dev] [RFC] igb_uio: change ISR to be threaded when using > with RT kernel >=20 > When igb_uio driver is used with RT kernel, the interrupt handler > should not use IRQF_NO_THREAD as a flag, since uio_event_notify will > call rt_spin_lock which might sleep. >=20 > Here is the calltrace. >=20 > [ 2034.457805] Call Trace: > [ 2034.460818] > [ 2034.463397] dump_stack+0x70/0x9a > [ 2034.467281] ___might_sleep.cold+0xe1/0xf2 > [ 2034.471943] rt_spin_lock+0x55/0x70 > [ 2034.475994] ? __wake_up_common_lock+0x61/0xb0 > [ 2034.481004] __wake_up_common_lock+0x61/0xb0 > [ 2034.485842] __wake_up+0x13/0x20 > [ 2034.489635] uio_event_notify+0x2c/0x50 [uio] > [ 2034.494560] igbuio_pci_irqhandler+0x1f/0x40 [igb_uio] > [ 2034.500262] __handle_irq_event_percpu+0x5f/0x3f0 > [ 2034.505532] ? cpuidle_enter_state+0xd3/0x500 > [ 2034.510454] handle_irq_event_percpu+0x4b/0x90 > [ 2034.515462] handle_irq_event+0x3c/0x5b > [ 2034.519864] handle_edge_irq+0xbb/0x210 > [ 2034.524264] handle_irq+0x23/0x30 > [ 2034.528143] do_IRQ+0x7e/0x150 > [ 2034.531764] common_interrupt+0xf/0xf > [ 2034.535990] >=20 > Signed-off-by: Yongxin Liu > --- > kernel/linux/igb_uio/igb_uio.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) >=20 > diff --git a/kernel/linux/igb_uio/igb_uio.c > b/kernel/linux/igb_uio/igb_uio.c > index 039f5a5f6..9d7380fb7 100644 > --- a/kernel/linux/igb_uio/igb_uio.c > +++ b/kernel/linux/igb_uio/igb_uio.c > @@ -221,7 +221,6 @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev > *udev) > msix_entry.entry =3D 0; > if (pci_enable_msix(udev->pdev, &msix_entry, 1) =3D=3D 0) { > dev_dbg(&udev->pdev->dev, "using MSI-X"); > - udev->info.irq_flags =3D IRQF_NO_THREAD; > udev->info.irq =3D msix_entry.vector; > udev->mode =3D RTE_INTR_MODE_MSIX; > break; > @@ -229,7 +228,6 @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev > *udev) > #else > if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) =3D=3D > 1) { > dev_dbg(&udev->pdev->dev, "using MSI-X"); > - udev->info.irq_flags =3D IRQF_NO_THREAD; > udev->info.irq =3D pci_irq_vector(udev->pdev, 0); > udev->mode =3D RTE_INTR_MODE_MSIX; > break; > @@ -241,7 +239,6 @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev > *udev) > #ifndef HAVE_ALLOC_IRQ_VECTORS > if (pci_enable_msi(udev->pdev) =3D=3D 0) { > dev_dbg(&udev->pdev->dev, "using MSI"); > - udev->info.irq_flags =3D IRQF_NO_THREAD; > udev->info.irq =3D udev->pdev->irq; > udev->mode =3D RTE_INTR_MODE_MSI; > break; > @@ -249,7 +246,6 @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev > *udev) > #else > if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) =3D=3D 1) > { > dev_dbg(&udev->pdev->dev, "using MSI"); > - udev->info.irq_flags =3D IRQF_NO_THREAD; > udev->info.irq =3D pci_irq_vector(udev->pdev, 0); > udev->mode =3D RTE_INTR_MODE_MSI; > break; > @@ -259,7 +255,7 @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev > *udev) > case RTE_INTR_MODE_LEGACY: > if (pci_intx_mask_supported(udev->pdev)) { > dev_dbg(&udev->pdev->dev, "using INTX"); > - udev->info.irq_flags =3D IRQF_SHARED | IRQF_NO_THREAD; > + udev->info.irq_flags =3D IRQF_SHARED; > udev->info.irq =3D udev->pdev->irq; > udev->mode =3D RTE_INTR_MODE_LEGACY; > break; > -- > 2.14.4