From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 7D467AFD7 for ; Tue, 15 Apr 2014 16:09:41 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 15 Apr 2014 07:03:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,864,1389772800"; d="scan'208";a="493516040" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by orsmga001.jf.intel.com with ESMTP; 15 Apr 2014 07:08:19 -0700 Received: from irsmsx107.ger.corp.intel.com (163.33.3.99) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.123.3; Tue, 15 Apr 2014 15:08:18 +0100 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.172]) by IRSMSX107.ger.corp.intel.com ([169.254.10.157]) with mapi id 14.03.0123.003; Tue, 15 Apr 2014 15:08:18 +0100 From: "Richardson, Bruce" To: David Marchand , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 1/2] mem: add write memory barrier before changing heap state Thread-Index: AQHPWLHkfekvSJVViEqnj2yzVb4EhZsSs8UQ Date: Tue, 15 Apr 2014 14:08:17 +0000 Message-ID: <59AF69C657FD0841A61C55336867B5B01A9FCCFF@IRSMSX103.ger.corp.intel.com> References: <1397569859-14460-1-git-send-email-david.marchand@6wind.com> In-Reply-To: <1397569859-14460-1-git-send-email-david.marchand@6wind.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 1/2] mem: add write memory barrier before changing heap state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Apr 2014 14:09:42 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of David Marchand > Sent: Tuesday, April 15, 2014 2:51 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH 1/2] mem: add write memory barrier before > changing heap state >=20 > From: Didier Pallard >=20 > a write memory barrier is needed before changing heap state value, else s= ome > concurrent core may see state changing before all initialization values a= re > written to memory, causing unpredictable results in malloc function. >=20 > Signed-off-by: Didier Pallard No barrier should be necessary here. As in a number of other places, such a= s rings, compiler barriers can be used in place of write memory barriers, d= ue to IA ordering rules. However, in this case, both variables referenced a= re volatile variables and so the assignments to them cannot be reordered by= the compiler so no compiler barrier is necessary either. Regards, /Bruce