From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35990A051C; Sun, 9 Feb 2020 13:26:18 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 428C21BEF2; Sun, 9 Feb 2020 13:26:17 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id B3F701BEDE for ; Sun, 9 Feb 2020 13:26:15 +0100 (CET) Received: from Internal Mail-Server by MTLPINE2 (envelope-from dekelp@mellanox.com) with ESMTPS (AES256-SHA encrypted); 9 Feb 2020 14:26:09 +0200 Received: from mtl-vdi-280.wap.labs.mlnx. (mtl-vdi-280.wap.labs.mlnx [10.128.130.87]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 019CQ9e7030126; Sun, 9 Feb 2020 14:26:09 +0200 From: Dekel Peled To: matan@mellanox.com, viacheslavo@mellanox.com, rasland@mellanox.com Cc: dev@dpdk.org Date: Sun, 9 Feb 2020 14:25:40 +0200 Message-Id: <5efd0f36d43342b0e450fed3642f2b2498cf0899.1581251023.git.dekelp@mellanox.com> X-Mailer: git-send-email 1.7.1 Subject: [dpdk-dev] [PATCH] net/mlx5: set VLAN tag matcher bit properly X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently MLX5 PMD can't match on untagged packets specifically. Tagged traffic still hits the flows intended for untagged packets. If the flow has ETH, it will catch all matching packets, tagged and untagged. The solution is to use cvlan_tag bit. If mask=1 and value=0 it matches on untagged traffic. If mask=1 and value=1 it matches on tagged traffic. This is the kernel implementation. This patch updated MLX5 PMD to set cvlan_tag mask and value according to flow rule contents. Signed-off-by: Dekel Peled --- drivers/net/mlx5/mlx5_flow_dv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3daabd3..a28af7c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5214,6 +5214,15 @@ struct field_modify_info modify_tcp[] = { rte_be_to_cpu_16(eth_m->type)); l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype); *(uint16_t *)(l24_v) = eth_m->type & eth_v->type; + if (eth_v->type) { + /* When ethertype is present set mask for tagged VLAN. */ + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); + /* Set value for tagged VLAN if ethertype is 802.1Q. */ + if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) || + eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) + MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, + 1); + } } /** @@ -5354,6 +5363,7 @@ struct field_modify_info modify_tcp[] = { ipv4_m->hdr.next_proto_id); MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); } /** @@ -5458,6 +5468,7 @@ struct field_modify_info modify_tcp[] = { ipv6_m->hdr.proto); MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, ipv6_v->hdr.proto & ipv6_m->hdr.proto); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); } /** -- 1.8.3.1