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From: Maxime Coquelin <maxime.coquelin@redhat.com>
To: Xueming Li <xuemingl@nvidia.com>, Matan Azrad <matan@nvidia.com>,
	Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Cc: dev@dpdk.org, Asaf Penso <asafp@nvidia.com>, stable@dpdk.org
Subject: Re: [dpdk-dev] [PATCH 2/2] vdpa/mlx5: specify lag port affinity
Date: Wed, 28 Oct 2020 10:35:17 +0100
Message-ID: <63f6bcfc-b826-91d0-627f-414403e1a722@redhat.com> (raw)
In-Reply-To: <1603710656-32187-2-git-send-email-xuemingl@nvidia.com>

On 10/26/20 12:10 PM, Xueming Li wrote:
> If set TIS lag port affinity to auto, firmware assign port affinity on
> each creation with Round Robin. In case of 2 PFs, if create virtq,
> destroy and create again, then each virtq will get same port affinity.
> To resolve this fw limitation, this patch sets create TIS with specified
> affinity for each PF.

OK, this patch describes better the issue the series is addressing.
Could you add a Fixes tag, so that it helps maintainers to backport it?

Other than that:
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>


> Cc: stable@dpdk.org
> Signed-off-by: Xueming Li <xuemingl@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
>  drivers/vdpa/mlx5/mlx5_vdpa.c       |  3 +++
>  drivers/vdpa/mlx5/mlx5_vdpa.h       |  3 ++-
>  drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 23 ++++++++++++++---------
>  3 files changed, 19 insertions(+), 10 deletions(-)

  reply	other threads:[~2020-10-28  9:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-26 11:10 [dpdk-dev] [PATCH 1/2] common/mlx5: get number of ports that can be bonded Xueming Li
2020-10-26 11:10 ` [dpdk-dev] [PATCH 2/2] vdpa/mlx5: specify lag port affinity Xueming Li
2020-10-28  9:35   ` Maxime Coquelin [this message]
2020-10-28 10:32     ` Xueming(Steven) Li
2020-10-28  9:30 ` [dpdk-dev] [PATCH 1/2] common/mlx5: get number of ports that can be bonded Maxime Coquelin
2020-10-28 10:44 ` [dpdk-dev] [PATCH v1 " Xueming Li
2020-10-29  8:29   ` Maxime Coquelin
2020-10-28 10:44 ` [dpdk-dev] [PATCH v1 2/2] vdpa/mlx5: specify lag port affinity Xueming Li
2020-10-29  8:29   ` Maxime Coquelin

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