* [dpdk-dev] [PATCH 1/3] doc: add CXGBEVF PMD documentation
2018-04-04 3:53 [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates Rahul Lakkireddy
@ 2018-04-04 3:53 ` Rahul Lakkireddy
2018-04-04 3:53 ` [dpdk-dev] [PATCH 2/3] net/cxgbe: add option to keep outer VLAN tag in Q-in-Q Rahul Lakkireddy
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Rahul Lakkireddy @ 2018-04-04 3:53 UTC (permalink / raw)
To: dev; +Cc: kumaras, shaguna, nirranjan, indranil
From: Kumar Sanghvi <kumaras@chelsio.com>
Add documentation on running DPDK on SR-IOV virtual functions for
Chelsio NICs.
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
---
doc/guides/nics/cxgbe.rst | 127 ++++++++++++++++++++++++++++++++++-
doc/guides/nics/features/cxgbevf.ini | 1 +
2 files changed, 127 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst
index f2e209901..a4a7c944a 100644
--- a/doc/guides/nics/cxgbe.rst
+++ b/doc/guides/nics/cxgbe.rst
@@ -9,13 +9,16 @@ The CXGBE PMD (**librte_pmd_cxgbe**) provides poll mode driver support
for **Chelsio Terminator** 10/25/40/100 Gbps family of adapters. CXGBE PMD
has support for the latest Linux and FreeBSD operating systems.
+CXGBEVF PMD provides poll mode driver support for SR-IOV Virtual functions
+and has support for the latest Linux operating systems.
+
More information can be found at `Chelsio Communications Official Website
<http://www.chelsio.com>`_.
Features
--------
-CXGBE PMD has support for:
+CXGBE and CXGBEVF PMD has support for:
- Multiple queues for TX and RX
- Receiver Side Steering (RSS)
@@ -39,6 +42,8 @@ port.
For this reason, one cannot whitelist/blacklist a single port without
whitelisting/blacklisting the other ports on the same device.
+.. _t5-nics:
+
Supported Chelsio T5 NICs
-------------------------
@@ -47,12 +52,20 @@ Supported Chelsio T5 NICs
- 40G NICs: T580-CR, T580-LP-CR, T580-SO-CR
- Other T5 NICs: T522-CR
+.. _t6-nics:
+
Supported Chelsio T6 NICs
-------------------------
- 25G NICs: T6425-CR, T6225-CR, T6225-LL-CR, T6225-SO-CR
- 100G NICs: T62100-CR, T62100-LP-CR, T62100-SO-CR
+Supported SR-IOV Chelsio NICs
+-----------------------------
+
+SR-IOV virtual functions are supported on all the Chelsio NICs listed
+in :ref:`t5-nics` and :ref:`t6-nics`.
+
Prerequisites
-------------
@@ -86,6 +99,10 @@ enabling debugging options may affect system performance.
Toggle compilation of librte_pmd_cxgbe driver.
+ .. note::
+
+ This controls compilation of both CXGBE and CXGBEVF PMD.
+
- ``CONFIG_RTE_LIBRTE_CXGBE_DEBUG`` (default **n**)
Toggle display of generic debugging messages.
@@ -262,6 +279,114 @@ devices managed by librte_pmd_cxgbe in Linux operating system.
Flow control pause TX/RX is disabled by default and can be enabled via
testpmd. Refer section :ref:`flow-control` for more details.
+Configuring SR-IOV Virtual Functions
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This section demonstrates how to enable SR-IOV virtual functions
+on Chelsio NICs and demonstrates how to run testpmd with SR-IOV
+virtual functions.
+
+#. Load the kernel module:
+
+ .. code-block:: console
+
+ modprobe cxgb4
+
+#. Get the PCI bus addresses of the interfaces bound to cxgb4 driver:
+
+ .. code-block:: console
+
+ dmesg | tail -2
+
+ Example output:
+
+ .. code-block:: console
+
+ cxgb4 0000:02:00.4 p1p1: renamed from eth0
+ cxgb4 0000:02:00.4 p1p2: renamed from eth1
+
+ .. note::
+
+ Both the interfaces of a Chelsio 2-port adapter are bound to the
+ same PCI bus address.
+
+#. Use ifconfig to get the interface name assigned to Chelsio card:
+
+ .. code-block:: console
+
+ ifconfig -a | grep "00:07:43"
+
+ Example output:
+
+ .. code-block:: console
+
+ p1p1 Link encap:Ethernet HWaddr 00:07:43:2D:EA:C0
+ p1p2 Link encap:Ethernet HWaddr 00:07:43:2D:EA:C8
+
+#. Bring up the interfaces:
+
+ .. code-block:: console
+
+ ifconfig p1p1 up
+ ifconfig p1p2 up
+
+#. Instantiate SR-IOV Virtual Functions. PF0..3 can be used for
+ SR-IOV VFs. Multiple VFs can be instantiated on each of PF0..3.
+ To instantiate one SR-IOV VF on each PF0 and PF1:
+
+ .. code-block:: console
+
+ echo 1 > /sys/bus/pci/devices/0000\:02\:00.0/sriov_numvfs
+ echo 1 > /sys/bus/pci/devices/0000\:02\:00.1/sriov_numvfs
+
+#. Get the PCI bus addresses of the virtual functions:
+
+ .. code-block:: console
+
+ lspci | grep -i "Chelsio" | grep -i "VF"
+
+ Example output:
+
+ .. code-block:: console
+
+ 02:01.0 Ethernet controller: Chelsio Communications Inc T540-CR Unified Wire Ethernet Controller [VF]
+ 02:01.1 Ethernet controller: Chelsio Communications Inc T540-CR Unified Wire Ethernet Controller [VF]
+
+#. Running testpmd
+
+ Follow instructions available in the document
+ :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
+ to bind virtual functions and run testpmd.
+
+ Example output:
+
+ .. code-block:: console
+
+ [...]
+ EAL: PCI device 0000:02:01.0 on NUMA socket 0
+ EAL: probe driver: 1425:5803 net_cxgbevf
+ PMD: rte_cxgbe_pmd: Firmware version: 1.17.14.0
+ PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.4.9
+ PMD: rte_cxgbe_pmd: Chelsio rev 0
+ PMD: rte_cxgbe_pmd: No bootstrap loaded
+ PMD: rte_cxgbe_pmd: No Expansion ROM loaded
+ PMD: rte_cxgbe_pmd: 0000:02:01.0 Chelsio rev 0 1G/10GBASE-SFP
+ EAL: PCI device 0000:02:01.1 on NUMA socket 0
+ EAL: probe driver: 1425:5803 net_cxgbevf
+ PMD: rte_cxgbe_pmd: Firmware version: 1.17.14.0
+ PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.4.9
+ PMD: rte_cxgbe_pmd: Chelsio rev 0
+ PMD: rte_cxgbe_pmd: No bootstrap loaded
+ PMD: rte_cxgbe_pmd: No Expansion ROM loaded
+ PMD: rte_cxgbe_pmd: 0000:02:01.1 Chelsio rev 0 1G/10GBASE-SFP
+ Configuring Port 0 (socket 0)
+ Port 0: 06:44:29:44:40:00
+ Configuring Port 1 (socket 0)
+ Port 1: 06:44:29:44:40:10
+ Checking link statuses...
+ Done
+ testpmd>
+
FreeBSD
-------
diff --git a/doc/guides/nics/features/cxgbevf.ini b/doc/guides/nics/features/cxgbevf.ini
index 7706106d1..b41fc3655 100644
--- a/doc/guides/nics/features/cxgbevf.ini
+++ b/doc/guides/nics/features/cxgbevf.ini
@@ -26,3 +26,4 @@ Linux UIO = Y
Linux VFIO = Y
x86-32 = Y
x86-64 = Y
+Usage doc = Y
--
2.14.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [dpdk-dev] [PATCH 2/3] net/cxgbe: add option to keep outer VLAN tag in Q-in-Q
2018-04-04 3:53 [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates Rahul Lakkireddy
2018-04-04 3:53 ` [dpdk-dev] [PATCH 1/3] doc: add CXGBEVF PMD documentation Rahul Lakkireddy
@ 2018-04-04 3:53 ` Rahul Lakkireddy
2018-04-04 3:53 ` [dpdk-dev] [PATCH 3/3] net/cxgbe: update to Rx/Tx offload API Rahul Lakkireddy
2018-04-05 17:22 ` [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates Ferruh Yigit
3 siblings, 0 replies; 5+ messages in thread
From: Rahul Lakkireddy @ 2018-04-04 3:53 UTC (permalink / raw)
To: dev; +Cc: kumaras, shaguna, nirranjan, indranil
From: Shagun Agrawal <shaguna@chelsio.com>
Add devargs option to keep outer VLAN tag in Q-in-Q packets.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
---
doc/guides/nics/cxgbe.rst | 16 ++++++++
drivers/net/cxgbe/base/t4_regs.h | 54 ++++++++++++++++++++++++++
drivers/net/cxgbe/cxgbe_main.c | 82 ++++++++++++++++++++++++++++++++++++++++
drivers/net/cxgbe/sge.c | 3 +-
4 files changed, 154 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst
index a4a7c944a..38d434802 100644
--- a/doc/guides/nics/cxgbe.rst
+++ b/doc/guides/nics/cxgbe.rst
@@ -127,6 +127,22 @@ enabling debugging options may affect system performance.
Toggle behaviour to prefer Throughput or Latency.
+Runtime Options
+~~~~~~~~~~~~~~~
+
+The following ``devargs`` options can be enabled at runtime. They must
+be passed as part of EAL arguments. For example,
+
+.. code-block:: console
+
+ testpmd -w 02:00.4,keep_ovlan=1 -- -i
+
+- ``keep_ovlan`` (default **0**)
+
+ Toggle behaviour to keep/strip outer VLAN in Q-in-Q packets. If
+ enabled, the outer VLAN tag is preserved in Q-in-Q packets. Otherwise,
+ the outer VLAN tag is stripped in Q-in-Q packets.
+
.. _driver-compilation:
Driver compilation and testing
diff --git a/drivers/net/cxgbe/base/t4_regs.h b/drivers/net/cxgbe/base/t4_regs.h
index 28ff21927..c0d6ddcac 100644
--- a/drivers/net/cxgbe/base/t4_regs.h
+++ b/drivers/net/cxgbe/base/t4_regs.h
@@ -571,6 +571,9 @@
#define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
#define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
+#define S_RM_OVLAN 9
+#define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
+
/* registers for module MPS */
#define MPS_BASE_ADDR 0x9000
#define T4VF_MPS_BASE_ADDR 0x0100
@@ -789,6 +792,57 @@
#define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
+#define A_MPS_PORT0_RX_IVLAN 0x3011c
+
+#define S_IVLAN_ETYPE 0
+#define M_IVLAN_ETYPE 0xffffU
+#define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
+
+#define MPS_PORT_RX_IVLAN_STRIDE 0x4000
+#define MPS_PORT_RX_IVLAN(idx) \
+ (A_MPS_PORT0_RX_IVLAN + (idx) * MPS_PORT_RX_IVLAN_STRIDE)
+
+#define A_MPS_PORT0_RX_OVLAN0 0x30120
+
+#define S_OVLAN_MASK 16
+#define M_OVLAN_MASK 0xffffU
+#define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
+
+#define S_OVLAN_ETYPE 0
+#define M_OVLAN_ETYPE 0xffffU
+#define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
+
+#define MPS_PORT_RX_OVLAN_STRIDE 0x4000
+#define MPS_PORT_RX_OVLAN_BASE(idx) \
+(A_MPS_PORT0_RX_OVLAN0 + (idx) * MPS_PORT_RX_OVLAN_STRIDE)
+#define MPS_PORT_RX_OVLAN_REG(idx, reg) (MPS_PORT_RX_OVLAN_BASE(idx) + (reg))
+
+#define A_RX_OVLAN0 0x0
+#define A_RX_OVLAN1 0x4
+#define A_RX_OVLAN2 0x8
+
+#define A_MPS_PORT0_RX_CTL 0x30100
+
+#define S_OVLAN_EN0 0
+#define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
+#define F_OVLAN_EN0 V_OVLAN_EN0(1)
+
+#define S_OVLAN_EN1 1
+#define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
+#define F_OVLAN_EN1 V_OVLAN_EN1(1)
+
+#define S_OVLAN_EN2 2
+#define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
+#define F_OVLAN_EN2 V_OVLAN_EN2(1)
+
+#define S_IVLAN_EN 4
+#define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
+#define F_IVLAN_EN V_IVLAN_EN(1)
+
+#define MPS_PORT_RX_CTL_STRIDE 0x4000
+#define MPS_PORT_RX_CTL(idx) \
+ (A_MPS_PORT0_RX_CTL + (idx) * MPS_PORT_RX_CTL_STRIDE)
+
/* registers for module ULP_RX */
#define ULP_RX_BASE_ADDR 0x19150
diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c
index 01a80ace8..c786a1a36 100644
--- a/drivers/net/cxgbe/cxgbe_main.c
+++ b/drivers/net/cxgbe/cxgbe_main.c
@@ -32,12 +32,15 @@
#include <rte_malloc.h>
#include <rte_random.h>
#include <rte_dev.h>
+#include <rte_kvargs.h>
#include "common.h"
#include "t4_regs.h"
#include "t4_msg.h"
#include "cxgbe.h"
+#define CXGBE_DEVARG_KEEP_OVLAN "keep_ovlan"
+
/*
* Response queue handler for the FW event queue.
*/
@@ -392,6 +395,84 @@ void print_port_info(struct adapter *adap)
}
}
+static int
+check_devargs_handler(__rte_unused const char *key, const char *value,
+ __rte_unused void *opaque)
+{
+ if (strcmp(value, "1"))
+ return -1;
+
+ return 0;
+}
+
+static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
+{
+ struct rte_kvargs *kvlist;
+
+ if (!devargs)
+ return 0;
+
+ kvlist = rte_kvargs_parse(devargs->args, NULL);
+ if (!kvlist)
+ return 0;
+
+ if (!rte_kvargs_count(kvlist, key)) {
+ rte_kvargs_free(kvlist);
+ return 0;
+ }
+
+ if (rte_kvargs_process(kvlist, key,
+ check_devargs_handler, NULL) < 0) {
+ rte_kvargs_free(kvlist);
+ return 0;
+ }
+ rte_kvargs_free(kvlist);
+
+ return 1;
+}
+
+static void configure_vlan_types(struct adapter *adapter)
+{
+ struct rte_pci_device *pdev = adapter->pdev;
+ int i;
+
+ for_each_port(adapter, i) {
+ /* OVLAN Type 0x88a8 */
+ t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
+ V_OVLAN_MASK(M_OVLAN_MASK) |
+ V_OVLAN_ETYPE(M_OVLAN_ETYPE),
+ V_OVLAN_MASK(M_OVLAN_MASK) |
+ V_OVLAN_ETYPE(0x88a8));
+ /* OVLAN Type 0x9100 */
+ t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
+ V_OVLAN_MASK(M_OVLAN_MASK) |
+ V_OVLAN_ETYPE(M_OVLAN_ETYPE),
+ V_OVLAN_MASK(M_OVLAN_MASK) |
+ V_OVLAN_ETYPE(0x9100));
+ /* OVLAN Type 0x8100 */
+ t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
+ V_OVLAN_MASK(M_OVLAN_MASK) |
+ V_OVLAN_ETYPE(M_OVLAN_ETYPE),
+ V_OVLAN_MASK(M_OVLAN_MASK) |
+ V_OVLAN_ETYPE(0x8100));
+
+ /* IVLAN 0X8100 */
+ t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
+ V_IVLAN_ETYPE(M_IVLAN_ETYPE),
+ V_IVLAN_ETYPE(0x8100));
+
+ t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
+ F_OVLAN_EN0 | F_OVLAN_EN1 |
+ F_OVLAN_EN2 | F_IVLAN_EN,
+ F_OVLAN_EN0 | F_OVLAN_EN1 |
+ F_OVLAN_EN2 | F_IVLAN_EN);
+ }
+
+ if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
+ t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
+ V_RM_OVLAN(1), V_RM_OVLAN(0));
+}
+
static void configure_pcie_ext_tag(struct adapter *adapter)
{
u16 v;
@@ -808,6 +889,7 @@ static int adap_init0(struct adapter *adap)
t4_init_sge_params(adap);
t4_init_tp_params(adap);
configure_pcie_ext_tag(adap);
+ configure_vlan_types(adap);
adap->params.drv_memwin = MEMWIN_NIC;
adap->flags |= FW_OK;
diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c
index 83e26d0c6..0d866354e 100644
--- a/drivers/net/cxgbe/sge.c
+++ b/drivers/net/cxgbe/sge.c
@@ -1596,7 +1596,8 @@ static int process_responses(struct sge_rspq *q, int budget,
}
if (cpl->vlan_ex) {
- pkt->ol_flags |= PKT_RX_VLAN;
+ pkt->ol_flags |= PKT_RX_VLAN |
+ PKT_RX_VLAN_STRIPPED;
pkt->vlan_tci = ntohs(cpl->vlan);
}
--
2.14.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [dpdk-dev] [PATCH 3/3] net/cxgbe: update to Rx/Tx offload API
2018-04-04 3:53 [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates Rahul Lakkireddy
2018-04-04 3:53 ` [dpdk-dev] [PATCH 1/3] doc: add CXGBEVF PMD documentation Rahul Lakkireddy
2018-04-04 3:53 ` [dpdk-dev] [PATCH 2/3] net/cxgbe: add option to keep outer VLAN tag in Q-in-Q Rahul Lakkireddy
@ 2018-04-04 3:53 ` Rahul Lakkireddy
2018-04-05 17:22 ` [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates Ferruh Yigit
3 siblings, 0 replies; 5+ messages in thread
From: Rahul Lakkireddy @ 2018-04-04 3:53 UTC (permalink / raw)
To: dev; +Cc: kumaras, shaguna, nirranjan, indranil
From: Shagun Agrawal <shaguna@chelsio.com>
Update to new Rx/Tx offload API. Always set CRC stripping during
configuration, since it can't be disabled.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
---
drivers/net/cxgbe/cxgbe_ethdev.c | 87 ++++++++++++++++++++++++++++++++--------
drivers/net/cxgbe/sge.c | 3 +-
2 files changed, 73 insertions(+), 17 deletions(-)
diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c
index feae01d6a..581a1f33a 100644
--- a/drivers/net/cxgbe/cxgbe_ethdev.c
+++ b/drivers/net/cxgbe/cxgbe_ethdev.c
@@ -58,6 +58,19 @@
*/
#include "t4_pci_id_tbl.h"
+#define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
+ DEV_TX_OFFLOAD_IPV4_CKSUM |\
+ DEV_TX_OFFLOAD_UDP_CKSUM |\
+ DEV_TX_OFFLOAD_TCP_CKSUM |\
+ DEV_TX_OFFLOAD_TCP_TSO)
+
+#define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
+ DEV_RX_OFFLOAD_CRC_STRIP |\
+ DEV_RX_OFFLOAD_IPV4_CKSUM |\
+ DEV_RX_OFFLOAD_JUMBO_FRAME |\
+ DEV_RX_OFFLOAD_UDP_CKSUM |\
+ DEV_RX_OFFLOAD_TCP_CKSUM)
+
uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts)
{
@@ -132,16 +145,11 @@ void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
device_info->max_vfs = adapter->params.arch.vfcount;
device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
- device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
- DEV_RX_OFFLOAD_IPV4_CKSUM |
- DEV_RX_OFFLOAD_UDP_CKSUM |
- DEV_RX_OFFLOAD_TCP_CKSUM;
+ device_info->rx_queue_offload_capa = 0UL;
+ device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
- device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
- DEV_TX_OFFLOAD_IPV4_CKSUM |
- DEV_TX_OFFLOAD_UDP_CKSUM |
- DEV_TX_OFFLOAD_TCP_CKSUM |
- DEV_TX_OFFLOAD_TCP_TSO;
+ device_info->tx_queue_offload_capa = 0UL;
+ device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
device_info->reta_size = pi->rss_size;
device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
@@ -229,9 +237,11 @@ int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
/* set to jumbo mode if needed */
if (new_mtu > ETHER_MAX_LEN)
- eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
+ eth_dev->data->dev_conf.rxmode.offloads |=
+ DEV_RX_OFFLOAD_JUMBO_FRAME;
else
- eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
+ eth_dev->data->dev_conf.rxmode.offloads &=
+ ~DEV_RX_OFFLOAD_JUMBO_FRAME;
err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
-1, -1, true);
@@ -358,9 +368,32 @@ int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
{
struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
struct adapter *adapter = pi->adapter;
+ uint64_t unsupported_offloads, configured_offloads;
int err;
CXGBE_FUNC_TRACE();
+ configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
+ if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
+ dev_info(adapter, "can't disable hw crc strip\n");
+ configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
+ }
+
+ unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS;
+ if (unsupported_offloads) {
+ dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. "
+ "Supported:0x%" PRIx64 "\n",
+ unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS);
+ return -ENOTSUP;
+ }
+
+ configured_offloads = eth_dev->data->dev_conf.txmode.offloads;
+ unsupported_offloads = configured_offloads & ~CXGBE_TX_OFFLOADS;
+ if (unsupported_offloads) {
+ dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. "
+ "Supported:0x%" PRIx64 "\n",
+ unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS);
+ return -ENOTSUP;
+ }
if (!(adapter->flags & FW_QUEUE_BOUND)) {
err = setup_sge_fwevtq(adapter);
@@ -417,8 +450,15 @@ int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
int err = 0;
unsigned int temp_nb_desc;
-
- RTE_SET_USED(tx_conf);
+ uint64_t unsupported_offloads;
+
+ unsupported_offloads = tx_conf->offloads & ~CXGBE_TX_OFFLOADS;
+ if (unsupported_offloads) {
+ dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. "
+ "Supported:0x%" PRIx64 "\n",
+ unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS);
+ return -ENOTSUP;
+ }
dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
__func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
@@ -527,8 +567,21 @@ int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
unsigned int temp_nb_desc;
struct rte_eth_dev_info dev_info;
unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
+ uint64_t unsupported_offloads, configured_offloads;
- RTE_SET_USED(rx_conf);
+ configured_offloads = rx_conf->offloads;
+ if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
+ dev_info(adapter, "can't disable hw crc strip\n");
+ configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
+ }
+
+ unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS;
+ if (unsupported_offloads) {
+ dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. "
+ "Supported:0x%" PRIx64 "\n",
+ unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS);
+ return -ENOTSUP;
+ }
dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
__func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
@@ -576,9 +629,11 @@ int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
/* Set to jumbo mode if necessary */
if (pkt_len > ETHER_MAX_LEN)
- eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
+ eth_dev->data->dev_conf.rxmode.offloads |=
+ DEV_RX_OFFLOAD_JUMBO_FRAME;
else
- eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
+ eth_dev->data->dev_conf.rxmode.offloads &=
+ ~DEV_RX_OFFLOAD_JUMBO_FRAME;
err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
&rxq->fl, t4_ethrx_handler,
diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c
index 0d866354e..a26712ae1 100644
--- a/drivers/net/cxgbe/sge.c
+++ b/drivers/net/cxgbe/sge.c
@@ -361,7 +361,8 @@ static unsigned int refill_fl_usembufs(struct adapter *adap, struct sge_fl *q,
struct rte_mbuf *buf_bulk[n];
int ret, i;
struct rte_pktmbuf_pool_private *mbp_priv;
- u8 jumbo_en = rxq->rspq.eth_dev->data->dev_conf.rxmode.jumbo_frame;
+ u8 jumbo_en = rxq->rspq.eth_dev->data->dev_conf.rxmode.offloads &
+ DEV_RX_OFFLOAD_JUMBO_FRAME;
/* Use jumbo mtu buffers if mbuf data room size can fit jumbo data. */
mbp_priv = rte_mempool_get_priv(rxq->rspq.mb_pool);
--
2.14.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates
2018-04-04 3:53 [dpdk-dev] [PATCH 0/3] cxgbe: Rx/Tx offload API, devargs, and doc updates Rahul Lakkireddy
` (2 preceding siblings ...)
2018-04-04 3:53 ` [dpdk-dev] [PATCH 3/3] net/cxgbe: update to Rx/Tx offload API Rahul Lakkireddy
@ 2018-04-05 17:22 ` Ferruh Yigit
3 siblings, 0 replies; 5+ messages in thread
From: Ferruh Yigit @ 2018-04-05 17:22 UTC (permalink / raw)
To: Rahul Lakkireddy, dev; +Cc: kumaras, shaguna, nirranjan, indranil
On 4/4/2018 4:53 AM, Rahul Lakkireddy wrote:
> Patch 1 updates document for CXGBEVF PMD.
>
> Patch 2 adds runtime devargs option to CXGBE PMD to keep/strip
> outer vlan in Q-in-Q packets.
>
> Patch 3 updates CXGBE PMD to use the new Rx/TX Offload API.
>
> Thanks,
> Rahul
>
> Kumar Sanghvi (1):
> doc: add CXGBEVF PMD documentation
>
> Shagun Agrawal (2):
> net/cxgbe: add option to keep outer VLAN tag in Q-in-Q
> net/cxgbe: update to Rx/Tx offload API
Series applied to dpdk-next-net/master, thanks.
^ permalink raw reply [flat|nested] 5+ messages in thread