From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DB7AA0579; Thu, 8 Apr 2021 16:10:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 47C6814101B; Thu, 8 Apr 2021 16:10:35 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id CAF684068B for ; Thu, 8 Apr 2021 16:10:33 +0200 (CEST) IronPort-SDR: u7jOTWWwpy2Ha5SRy7tH4tIlokxJZgnkwUXgqMyC/Xv3haAC6duw0MgiKCgyJMrec2zAmmWmh3 /RjdVImxsZHA== X-IronPort-AV: E=McAfee;i="6000,8403,9948"; a="193089768" X-IronPort-AV: E=Sophos;i="5.82,206,1613462400"; d="scan'208";a="193089768" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2021 07:10:32 -0700 IronPort-SDR: OtMcmx5XobL+60vATdhe32AL4u4womX/q51/bkc78/U+cmQmi56RbINzAO+cWsS2dF1NBxmpuC Aly/0h1tlFhw== X-IronPort-AV: E=Sophos;i="5.82,206,1613462400"; d="scan'208";a="380265549" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.203.5]) ([10.213.203.5]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2021 07:10:29 -0700 To: Raslan Darawsheh , Olivier Matz Cc: "dev@dpdk.org" , Ori Kam , "andrew.rybchenko@oktetlabs.ru" , "ivan.malov@oktetlabs.ru" , "ying.a.wang@intel.com" , Slava Ovsiienko , Shiri Kuzin References: <20210330075036.6579-2-rasland@nvidia.com> <20210404074552.24190-1-rasland@nvidia.com> <20210404074552.24190-2-rasland@nvidia.com> <20210408122956.GX1650@platinum> From: Ferruh Yigit X-User: ferruhy Message-ID: <65a77b53-03fa-3989-c688-60324552aabd@intel.com> Date: Thu, 8 Apr 2021 15:10:26 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v4 1/2] ethdev: add new ext hdr for gtp psc X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 4/8/2021 1:37 PM, Raslan Darawsheh wrote: > Hi Olivier, > >> -----Original Message----- >> From: Olivier Matz >> Sent: Thursday, April 8, 2021 3:30 PM >> To: Raslan Darawsheh >> Cc: dev@dpdk.org; ferruh.yigit@intel.com; Ori Kam ; >> andrew.rybchenko@oktetlabs.ru; ivan.malov@oktetlabs.ru; >> ying.a.wang@intel.com; Slava Ovsiienko ; Shiri >> Kuzin >> Subject: Re: [PATCH v4 1/2] ethdev: add new ext hdr for gtp psc >> >> Hi Raslan, >> >> On Sun, Apr 04, 2021 at 10:45:51AM +0300, Raslan Darawsheh wrote: >>> Define new rte header for gtp PDU session container >>> based on RFC 38415-g30 >> >> Do you have a link to this RFC? > Yes sure, > https://www.3gpp.org/ftp/Specs/archive/38_series/38.415/38415-g30.zip > >> >>> Signed-off-by: Raslan Darawsheh >>> --- >>> lib/librte_net/rte_gtp.h | 34 ++++++++++++++++++++++++++++++++++ >>> 1 file changed, 34 insertions(+) >>> >>> diff --git a/lib/librte_net/rte_gtp.h b/lib/librte_net/rte_gtp.h >>> index 6a6f9b238d..088b0b5a53 100644 >>> --- a/lib/librte_net/rte_gtp.h >>> +++ b/lib/librte_net/rte_gtp.h >>> @@ -61,6 +61,40 @@ struct rte_gtp_hdr_ext_word { >>> uint8_t next_ext; /**< Next Extension Header Type. */ >>> } __rte_packed; >>> >>> +/** >>> + * Optional extension for GTP with next_ext set to 0x85 >>> + * defined based on RFC 38415-g30. >>> + */ >>> +__extension__ >>> +struct rte_gtp_psc_hdr { >>> + uint8_t ext_hdr_len; /**< PDU ext hdr len in multiples of 4 bytes */ >>> + uint8_t type:4; /**< PDU type */ >>> + uint8_t qmp:1; /**< Qos Monitoring Packet */ >>> + union { >>> + struct { >>> + uint8_t snp:1; /**< Sequence number presence */ >>> + uint8_t spare_dl1:2; /**< spare down link bits */ >>> + }; >>> + struct { >>> + uint8_t dl_delay_ind:1; /**< dl delay result presence >> */ >>> + uint8_t ul_delay_ind:1; /**< ul delay result presence >> */ >>> + uint8_t snp_ul1:1; /**< Sequence number presence >> ul */ >>> + }; >>> + }; >>> + union { >>> + struct { >>> + uint8_t ppp:1; /**< Paging policy presence */ >>> + uint8_t rqi:1; /**< Reflective Qos Indicator */ >>> + }; >>> + struct { >>> + uint8_t n_delay_ind:1; /**< N3/N9 delay result >> presence */ >>> + uint8_t spare_ul2:1; /**< spare up link bits */ >>> + }; >>> + }; >>> + uint8_t qfi:6; /**< Qos Flow Identifier */ >>> + uint8_t data[0]; /**< data feilds */ >>> +} __rte_packed; >> >> With this header, sizeof(rte_gtp_psc_hdr) = 5, is it really expected? > The data[0] is variable length data, I guess I should send another version to mention that in the comment maybe. > The header size according to the spec should be 4 octets aligned in general. The struct is 5 btyes, this is not related to data[0], please check the pahole output: http://inbox.dpdk.org/dev/536631b9-c634-ddac-c154-91978ffc29a5@intel.com/ >> >> It would help to see the specification to have a better idea of how to > Sure, I've just posted the link above, please let me know of any suggestion that you have, and I'll be glad to do accordingly. > >> split, but a possible solution is to do something like this: >> >> struct rte_gtp_psc_generic_hdr { >> uint8_t ext_hdr_len; >> uint8_t type:4 >> uint8_t qmp:1; >> uint8_t pad:3; >> }; >> >> struct rte_gtp_psc__hdr { >> uint8_t ext_hdr_len; >> uint8_t type:4 >> uint8_t qmp:1; >> uint8_t uint8_t snp:1; >> uint8_t spare_dl1:2; >> ... >> }; >> >> ... >> >> struct rte_gtp_psc_hdr { >> union { >> struct rte_gtp_psc_generic_hdr generic; >> struct rte_gtp_psc__hdr ; >> struct rte_gtp_psc__hdr ; >> }; >> }; >> >> Also, you need to take care about endianness. >> >> >> Regards, >> Olivier > Kindest regards > Raslan Darawsheh >