From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85C1A454EF; Tue, 25 Jun 2024 13:29:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E94FA4326C; Tue, 25 Jun 2024 13:20:20 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id E767B42F4D for ; Tue, 25 Jun 2024 13:18:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314284; x=1750850284; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i5k2pbqUTNTBR0dDIDou2gi4Q3Q+hcZgzVZLjkQPVz0=; b=QCRMs9HgEYqHbxii4pbfi2NSePRR3MjBhGyhxRVMC0VBEwjpOfJmNZYS EcllKU6xLzXvrOZ+JzO1XNTNSUIRgHpY/P20Fq9YRVUrDk+weeUi9+dox RobFHq2QK5Jx8oPc7Lku/YLGLwiD/oNCVZhof4Is9rz6pwOorNlZRc22+ yptA7NQBHqeWDRx4l9P4MXr4iO23bpzzaeDAPlFuNCj3LRxXTCAx2WzZJ yeMRFDv4j0vUlAKr3HvWl6dznLBOuUCwF91a/wpFDxfOmwb+v4YbvutYW kEuW7mITsEQJReUp8mlsi3PMs4liwQsxmCwm4n26U1SGrxN4SsYNOmi/r w==; X-CSE-ConnectionGUID: TlgWCGYVR2qb9AdHV+hxPg== X-CSE-MsgGUID: D1PVX5NiTuC1Z1hJnG4s4w== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080631" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080631" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:03 -0700 X-CSE-ConnectionGUID: pspnmwT3RyGmwPQUuvLQcw== X-CSE-MsgGUID: 1quPx1BYSNC9Zep2X6nAgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719737" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:03 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Fabio Pricoco , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 114/129] net/ice/base: use a variable to store reset count Date: Tue, 25 Jun 2024 12:13:59 +0100 Message-ID: <6692c18a92d8f30c88ee4f84f3d20fb3fd81ddde.1719313663.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Fabio Pricoco Depending on platform and whether silicon validation tools are used, the timeout value may be set to a different value. This patch uses a variable to store the reset count value as opposed to using the macro directly. Signed-off-by: Fabio Pricoco Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_common.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 5d943dfa2e..ad9b95f75e 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1137,7 +1137,7 @@ void ice_deinit_hw(struct ice_hw *hw) */ int ice_check_reset(struct ice_hw *hw) { - u32 cnt, reg = 0, grst_timeout, uld_mask; + u32 cnt, reg = 0, grst_timeout, uld_mask, reset_wait_cnt; /* Poll for Device Active state in case a recent CORER, GLOBR, * or EMPR has occurred. The grst delay value is in 100ms units. @@ -1168,8 +1168,10 @@ int ice_check_reset(struct ice_hw *hw) uld_mask = ICE_RESET_DONE_MASK; + reset_wait_cnt = ICE_PF_RESET_WAIT_COUNT; + /* Device is Active; check Global Reset processes are done */ - for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { + for (cnt = 0; cnt < reset_wait_cnt; cnt++) { reg = rd32(hw, GLNVM_ULD) & uld_mask; if (reg == uld_mask) { ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); @@ -1178,7 +1180,7 @@ int ice_check_reset(struct ice_hw *hw) ice_msec_delay(10, true); } - if (cnt == ICE_PF_RESET_WAIT_COUNT) { + if (cnt == reset_wait_cnt) { ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", reg); return ICE_ERR_RESET_FAILED; @@ -1196,7 +1198,7 @@ int ice_check_reset(struct ice_hw *hw) */ static int ice_pf_reset(struct ice_hw *hw) { - u32 cnt, reg; + u32 cnt, reg, reset_wait_cnt, cfg_lock_timeout; /* If at function entry a global reset was already in progress, i.e. * state is not 'device active' or any of the reset done bits are not @@ -1221,8 +1223,10 @@ static int ice_pf_reset(struct ice_hw *hw) * timeout plus the PFR timeout which will account for a possible reset * that is occurring during a download package operation. */ - for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + - ICE_PF_RESET_WAIT_COUNT; cnt++) { + reset_wait_cnt = ICE_PF_RESET_WAIT_COUNT; + cfg_lock_timeout = ICE_GLOBAL_CFG_LOCK_TIMEOUT; + + for (cnt = 0; cnt < cfg_lock_timeout + reset_wait_cnt; cnt++) { reg = rd32(hw, PFGEN_CTRL); if (!(reg & PFGEN_CTRL_PFSWR_M)) break; @@ -1230,7 +1234,7 @@ static int ice_pf_reset(struct ice_hw *hw) ice_msec_delay(1, true); } - if (cnt == ICE_PF_RESET_WAIT_COUNT) { + if (cnt == cfg_lock_timeout + reset_wait_cnt) { ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); return ICE_ERR_RESET_FAILED; } -- 2.43.0