From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 32DD6A0548; Mon, 26 Apr 2021 14:21:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EAB7F411BC; Mon, 26 Apr 2021 14:21:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 211D1411C8 for ; Mon, 26 Apr 2021 14:21:32 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13QCFt6J019500 for ; Mon, 26 Apr 2021 05:21:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=chiNgEPozx2IMMpvYQu5wULbS3y8/wONpevQ1nVo9wQ=; b=eBK9gSiXhUmk1PHF+FaZweG8Lt3Ml//7rXIq+Xpil3qS2sJbQhwZCbm/uoEnrzjkSJ7O RoAE5tv+Sh1GkQ6gU6xIdjGZIsLuWdRwehigyagPnxSIfh3FEaufjfw0PBoWxPAkybFF ttAu/CABsiMd1ePf0vQiOwL1/cKx+4qOsSWalJr9kLfuMcNM2gjwtfQ/9xFXRKXow9na BGRhOnZwMqbFAnS/nsoLJKuKfTNP8VJh9qIpGxfzuRBrxjwXddz0Jp4r9TQc3xT81tk8 rwcFyxIg8mI96SS4K6sW2t8z/gYqmQiUoWpkUTGuBxbZ+vTV0q/PLL0S3exCPM/gRzHJ LA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 385hfr1s3h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 26 Apr 2021 05:21:32 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Apr 2021 05:21:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Apr 2021 05:21:30 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id AB5C03F703F; Mon, 26 Apr 2021 05:21:28 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , Jerin Jacob , Anoob Joseph , Ankur Dwivedi , Pavan Nikhilesh Date: Mon, 26 Apr 2021 17:51:07 +0530 Message-ID: <66a5cdfce8b20d07596c44c448029aefbbf7fe58.1619439044.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 3DsU-bTrZXfE7uPOhfNE_yNgDGfJji9i X-Proofpoint-GUID: 3DsU-bTrZXfE7uPOhfNE_yNgDGfJji9i X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-26_05:2021-04-26, 2021-04-26 signatures=0 Subject: [dpdk-dev] [PATCH v2 2/2] event/octeontx2: configure crypto adapter xaq pool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Configure xaq pool based on number of in-use crypto queues to avoid CPT add work failure due to xaq buffer run out. This patch configures OTX2_CPT_DEFAULT_CMD_QLEN number of xae entries per queue pair. Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework") Signed-off-by: Shijith Thotton Acked-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev_adptr.c | 2 +- drivers/event/octeontx2/otx2_evdev_crypto_adptr.c | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c index d69f269df..d85c3665c 100644 --- a/drivers/event/octeontx2/otx2_evdev_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_adptr.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(C) 2019 Marvell International Ltd. + * Copyright(C) 2019-2021 Marvell. */ #include "otx2_evdev.h" diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c index ed600a659..d9a002625 100644 --- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -89,6 +89,14 @@ otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F; sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); + /* Update crypto adapter xae count */ + if (queue_pair_id == -1) + sso_evdev->adptr_xae_cnt += + vf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN; + else + sso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN; + sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev); + return 0; } -- 2.25.1