From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 6E57F5F5D for ; Wed, 14 Mar 2018 16:46:53 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Mar 2018 08:46:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,470,1515484800"; d="scan'208";a="33826109" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by FMSMGA003.fm.intel.com with ESMTP; 14 Mar 2018 08:46:50 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.9]) by IRSMSX102.ger.corp.intel.com ([169.254.2.10]) with mapi id 14.03.0319.002; Wed, 14 Mar 2018 15:46:49 +0000 From: "Rybalchenko, Kirill" To: "Xing, Beilei" , "Zhang, Qi Z" CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] net/i40e: add log when setting input set Thread-Index: AQHTowVTlzmRAK9tKk21Uvq6w5SWm6PQEMkQ Date: Wed, 14 Mar 2018 15:46:49 +0000 Message-ID: <696B43C21188DF4F9C9091AAE4789B824E2D65F4@IRSMSX108.ger.corp.intel.com> References: <1518332150-85375-1-git-send-email-beilei.xing@intel.com> In-Reply-To: <1518332150-85375-1-git-send-email-beilei.xing@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDU3NzhlNGMtZDUwNi00NDA5LTgwMWYtYWIzYzY3ZDEzZGU3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IlZ2M01aUFp6T3RTOWJkZXFhSUhGcnBQME9tcXpIY1JhOE94akx4Mm5JZ1U9In0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: add log when setting input set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Mar 2018 15:46:55 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Beilei Xing > Sent: Sunday 11 February 2018 06:56 > To: Zhang, Qi Z > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] net/i40e: add log when setting input set >=20 > This patch adds log when setting input set since global configuration is > changed. >=20 > Signed-off-by: Beilei Xing > --- > drivers/net/i40e/rte_pmd_i40e.c | 30 +++++++++++++++++++++--------- > 1 file changed, 21 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/net/i40e/rte_pmd_i40e.c > b/drivers/net/i40e/rte_pmd_i40e.c index dae59e6..1288c51 100644 > --- a/drivers/net/i40e/rte_pmd_i40e.c > +++ b/drivers/net/i40e/rte_pmd_i40e.c > @@ -3071,6 +3071,7 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t > pctype, { > struct rte_eth_dev *dev; > struct i40e_hw *hw; > + struct i40e_pf *pf; > uint64_t inset_reg; > uint32_t mask_reg[2]; > int i; > @@ -3086,6 +3087,12 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t > pctype, > return -EINVAL; >=20 > hw =3D I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); > + > + if (pf->support_multi_driver) { > + PMD_DRV_LOG(ERR, "Input set configuration is not > supported."); > + return -ENOTSUP; > + } >=20 > /* Clear mask first */ > for (i =3D 0; i < 2; i++) > @@ -3098,14 +3105,17 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t > pctype, >=20 > switch (inset_type) { > case INSET_HASH: > - i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, > pctype), > - (uint32_t)(inset_reg & UINT32_MAX)); > - i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, > pctype), > - (uint32_t)((inset_reg >> > - I40E_32_BIT_WIDTH) & > UINT32_MAX)); > + i40e_check_write_global_reg(hw, > I40E_GLQF_HASH_INSET(0, pctype), > + (uint32_t)(inset_reg & > UINT32_MAX)); > + i40e_check_write_global_reg(hw, > I40E_GLQF_HASH_INSET(1, pctype), > + (uint32_t)((inset_reg >> > + I40E_32_BIT_WIDTH) & > UINT32_MAX)); > for (i =3D 0; i < 2; i++) > - i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, > pctype), > - mask_reg[i]); > + i40e_check_write_global_reg(hw, > + I40E_GLQF_HASH_MSK(i, > pctype), > + mask_reg[i]); > + i40e_global_cfg_warning(I40E_WARNING_HASH_INSET); > + i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); > break; > case INSET_FDIR: > i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, > 0), @@ -3114,8 +3124,10 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t > pctype, > (uint32_t)((inset_reg >> > I40E_32_BIT_WIDTH) & > UINT32_MAX)); > for (i =3D 0; i < 2; i++) > - i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, > pctype), > - mask_reg[i]); > + i40e_check_write_global_reg(hw, > + I40E_GLQF_FD_MSK(i, > pctype), > + mask_reg[i]); > + i40e_global_cfg_warning(I40E_WARNING_FD_MSK); > break; > case INSET_FDIR_FLX: > i40e_check_write_reg(hw, > I40E_PRTQF_FD_FLXINSET(pctype), > -- > 2.5.5 Reviewed-by: Kirill Rybalchenko