From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 1F137324A for ; Mon, 27 Nov 2017 20:58:02 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2017 11:58:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,465,1505804400"; d="scan'208";a="6888240" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.241.225.168]) ([10.241.225.168]) by orsmga003.jf.intel.com with ESMTP; 27 Nov 2017 11:58:01 -0800 To: Andrew Rybchenko , dev@dpdk.org Cc: Andrew Jackson References: <1510819481-6809-1-git-send-email-arybchenko@solarflare.com> <1510819481-6809-2-git-send-email-arybchenko@solarflare.com> From: Ferruh Yigit Message-ID: <69a7d813-9443-0a1b-5fef-432260439aa3@intel.com> Date: Mon, 27 Nov 2017 11:58:01 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <1510819481-6809-2-git-send-email-arybchenko@solarflare.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH 01/53] net/sfc/base: copy new header from firmwaresrc X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Nov 2017 19:58:03 -0000 On 11/16/2017 12:03 AM, Andrew Rybchenko wrote: > From: Andrew Jackson > > Signed-off-by: Andrew Jackson > Signed-off-by: Andrew Rybchenko > --- > drivers/net/sfc/base/siena_flash.h | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/sfc/base/siena_flash.h b/drivers/net/sfc/base/siena_flash.h > index e2700554..5fa3ea4 100644 > --- a/drivers/net/sfc/base/siena_flash.h > +++ b/drivers/net/sfc/base/siena_flash.h > @@ -113,15 +113,21 @@ typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ > efx_word_t checksum; /* of whole header area + firmware image */ > efx_word_t firmware_version_d; > efx_byte_t mcfw_subtype; > - efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */ > + efx_byte_t generation; /* MC (Medford and later): MC partition generation when */ > + /* written to NVRAM. */ > + /* MUM & SUC images: subtype. */ > + /* (Otherwise set to 0) */ > efx_dword_t firmware_text_offset; /* offset to firmware .text */ > efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ > efx_dword_t firmware_data_offset; /* offset to firmware .data */ > efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ > efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ > efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ > - efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */ > - efx_dword_t reserved_c[7]; /* (set to 0) */ > + efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */ > + /* the key, or 0xffff if unsigned. (Otherwise set to 0) */ > + efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */ Does this means there is a new updated FW? Should user know about version of it, or is FW upgrade needs to be documented somewhere? > + efx_byte_t reserved_b[3]; /* (set to 0) */ > + efx_dword_t reserved_c[6]; /* (set to 0) */ > } siena_mc_boot_hdr_t; > > #define SIENA_MC_BOOT_HDR_PADDING \ >