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From: "Lu, Wenzhuo" <wenzhuo.lu@intel.com>
To: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>, "dev@dpdk.org"
<dev@dpdk.org>
Thread-Topic: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update
Thread-Index: AQHRB5zthmJre+LN1UGkpbNMDoIh7Z5tUbig
Date: Fri, 16 Oct 2015 01:21:44 +0000
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Subject: Re: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update
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Hi Konstantin,
> -----Original Message-----
> From: Ananyev, Konstantin
> Sent: Friday, October 16, 2015 6:58 AM
> To: Lu, Wenzhuo; dev@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update
>=20
>=20
>=20
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu
> > Sent: Monday, September 28, 2015 8:53 AM
> > To: dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update
> >
> > This patch implements the VF RSS redirection table query and update
> > function on 10G NICs. But the update function is only provided for
> > x550. Because the other NICs don't have the separate registers for VF,
> > we don't want to let a VF NIC change the shared RSS reta registers. It =
may
> cause PF and other VF NICs'
> > behavior change without being noticed.
> >
> > Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
> > ---
> > drivers/net/ixgbe/ixgbe_ethdev.c | 103
> > +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 103 insertions(+)
> >
> > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c
> > b/drivers/net/ixgbe/ixgbe_ethdev.c
> > index 5e50ee6..44baadf 100644
> > --- a/drivers/net/ixgbe/ixgbe_ethdev.c
> > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
> > @@ -326,6 +326,13 @@ static int
> > ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, static int
> ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
> > struct timespec *timestamp);
> >
> > +static int ixgbevf_dev_rss_reta_update(struct rte_eth_dev *dev,
> > + struct rte_eth_rss_reta_entry64 *reta_conf,
> > + uint16_t reta_size);
> > +static int ixgbevf_dev_rss_reta_query(struct rte_eth_dev *dev,
> > + struct rte_eth_rss_reta_entry64 *reta_conf,
> > + uint16_t reta_size);
> > +
> > /*
> > * Define VF Stats MACRO for Non "cleared on read" register
> > */
> > @@ -497,6 +504,8 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops
> =3D {
> > .mac_addr_set =3D ixgbevf_set_default_mac_addr,
> > .get_reg_length =3D ixgbevf_get_reg_length,
> > .get_reg =3D ixgbevf_get_regs,
> > + .reta_update =3D ixgbevf_dev_rss_reta_update,
> > + .reta_query =3D ixgbevf_dev_rss_reta_query,
> > .rss_hash_update =3D ixgbevf_dev_rss_hash_update,
> > .rss_hash_conf_get =3D ixgbevf_dev_rss_hash_conf_get,
> > };
> > @@ -5557,6 +5566,100 @@ ixgbe_set_eeprom(struct rte_eth_dev *dev,
> > return eeprom->ops.write_buffer(hw, first, length, data); }
> >
> > +static int
> > +ixgbevf_dev_rss_reta_update(struct rte_eth_dev *dev,
> > + struct rte_eth_rss_reta_entry64 *reta_conf,
> > + uint16_t reta_size)
> > +{
> > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data-
> >dev_private);
> > + uint32_t reta, r;
> > + uint16_t i, j;
> > + uint16_t idx, shift;
> > + uint8_t mask;
> > +
> > + if (hw->mac.type !=3D ixgbe_mac_X550_vf &&
> > + hw->mac.type !=3D ixgbe_mac_X550EM_x_vf) {
> > + PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
> > + "VF NIC.");
> > + return -ENOTSUP;
> > + }
> > +
> > + if (reta_size !=3D ETH_RSS_RETA_SIZE_64) {
> > + PMD_DRV_LOG(ERR, "The size of hash lookup table configured
> "
> > + "(%d) doesn't match the number of hardware can "
> > + "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
> > + return -EINVAL;
> > + }
> > +
> > + for (i =3D 0; i < reta_size; i +=3D IXGBE_4_BIT_WIDTH) {
> > + idx =3D i / RTE_RETA_GROUP_SIZE;
> > + shift =3D i % RTE_RETA_GROUP_SIZE;
> > + mask =3D (uint8_t)((reta_conf[idx].mask >> shift) &
> > + IXGBE_4_BIT_WIDTH);
> > + if (!mask)
> > + continue;
> > + if (mask =3D=3D IXGBE_4_BIT_WIDTH)
> > + r =3D 0;
> > + else
> > + r =3D IXGBE_READ_REG(hw, IXGBE_VFRETA(i >> 2));
> > +
> > + for (j =3D 0, reta =3D 0; j < IXGBE_4_BIT_WIDTH; j++) {
> > + if (mask & (0x1 << j))
> > + reta |=3D reta_conf[idx].reta[shift + j] <<
> > + (CHAR_BIT * j);
> > + else
> > + reta |=3D r &
> > + (IXGBE_8_BIT_MASK << (CHAR_BIT * j));
> > + }
> > + IXGBE_WRITE_REG(hw, IXGBE_VFRETA(i >> 2), reta);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +ixgbevf_dev_rss_reta_query(struct rte_eth_dev *dev,
> > + struct rte_eth_rss_reta_entry64 *reta_conf,
> > + uint16_t reta_size)
> > +{
> > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data-
> >dev_private);
> > + uint32_t reta;
> > + uint16_t i, j;
> > + uint16_t idx, shift;
> > + uint8_t mask;
> > +
> > + if (hw->mac.type !=3D ixgbe_mac_X550_vf &&
> > + hw->mac.type !=3D ixgbe_mac_X550EM_x_vf) {
> > + return ixgbe_dev_rss_reta_query(dev, reta_conf, reta_size);
> > + }
> > +
> > + if (reta_size !=3D ETH_RSS_RETA_SIZE_64) {
> > + PMD_DRV_LOG(ERR, "The size of hash lookup table configured
> "
> > + "(%d) doesn't match the number of hardware can "
> > + "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
> > + return -EINVAL;
> > + }
> > +
> > + for (i =3D 0; i < reta_size; i +=3D IXGBE_4_BIT_WIDTH) {
> > + idx =3D i / RTE_RETA_GROUP_SIZE;
> > + shift =3D i % RTE_RETA_GROUP_SIZE;
> > + mask =3D (uint8_t)((reta_conf[idx].mask >> shift) &
> > + IXGBE_4_BIT_MASK);
> > + if (!mask)
> > + continue;
> > +
> > + reta =3D IXGBE_READ_REG(hw, IXGBE_VFRETA(i >> 2));
> > + for (j =3D 0; j < IXGBE_4_BIT_WIDTH; j++) {
> > + if (mask & (0x1 << j))
> > + reta_conf[idx].reta[shift + j] =3D
> > + ((reta >> (CHAR_BIT * j)) &
> > + IXGBE_8_BIT_MASK);
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
>=20
> Same as for other 3 patches in that series: >90% of the code is just copy=
& paste
> of existing one, with different HW registers name and reta_size.
> Pls unify.
> Konstantin
Thanks. I'll try to condense the code. And the same for the other 3 patches=
.
>=20
> > static struct rte_driver rte_ixgbe_driver =3D {
> > .type =3D PMD_PDEV,
> > .init =3D rte_ixgbe_pmd_init,
> > --
> > 1.9.3