From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id E7FA09208 for ; Fri, 16 Oct 2015 03:22:05 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 15 Oct 2015 18:21:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,687,1437462000"; d="scan'208";a="665406158" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 15 Oct 2015 18:21:47 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 15 Oct 2015 18:21:47 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 15 Oct 2015 18:21:47 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.253]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.106]) with mapi id 14.03.0248.002; Fri, 16 Oct 2015 09:21:45 +0800 From: "Lu, Wenzhuo" To: "Ananyev, Konstantin" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update Thread-Index: AQHRB5zthmJre+LN1UGkpbNMDoIh7Z5tUbig Date: Fri, 16 Oct 2015 01:21:44 +0000 Message-ID: <6A0DE07E22DDAD4C9103DF62FEBC09090209F5AF@shsmsx102.ccr.corp.intel.com> References: <1443426751-4906-1-git-send-email-wenzhuo.lu@intel.com> <1443426751-4906-5-git-send-email-wenzhuo.lu@intel.com> <2601191342CEEE43887BDE71AB97725836AB0358@irsmsx105.ger.corp.intel.com> In-Reply-To: <2601191342CEEE43887BDE71AB97725836AB0358@irsmsx105.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Oct 2015 01:22:07 -0000 Hi Konstantin, > -----Original Message----- > From: Ananyev, Konstantin > Sent: Friday, October 16, 2015 6:58 AM > To: Lu, Wenzhuo; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update >=20 >=20 >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu > > Sent: Monday, September 28, 2015 8:53 AM > > To: dev@dpdk.org > > Subject: [dpdk-dev] [PATCH 4/4] ixgbe: VF RSS reta query and update > > > > This patch implements the VF RSS redirection table query and update > > function on 10G NICs. But the update function is only provided for > > x550. Because the other NICs don't have the separate registers for VF, > > we don't want to let a VF NIC change the shared RSS reta registers. It = may > cause PF and other VF NICs' > > behavior change without being noticed. > > > > Signed-off-by: Wenzhuo Lu > > --- > > drivers/net/ixgbe/ixgbe_ethdev.c | 103 > > +++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 103 insertions(+) > > > > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c > > b/drivers/net/ixgbe/ixgbe_ethdev.c > > index 5e50ee6..44baadf 100644 > > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > > @@ -326,6 +326,13 @@ static int > > ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, static int > ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, > > struct timespec *timestamp); > > > > +static int ixgbevf_dev_rss_reta_update(struct rte_eth_dev *dev, > > + struct rte_eth_rss_reta_entry64 *reta_conf, > > + uint16_t reta_size); > > +static int ixgbevf_dev_rss_reta_query(struct rte_eth_dev *dev, > > + struct rte_eth_rss_reta_entry64 *reta_conf, > > + uint16_t reta_size); > > + > > /* > > * Define VF Stats MACRO for Non "cleared on read" register > > */ > > @@ -497,6 +504,8 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops > =3D { > > .mac_addr_set =3D ixgbevf_set_default_mac_addr, > > .get_reg_length =3D ixgbevf_get_reg_length, > > .get_reg =3D ixgbevf_get_regs, > > + .reta_update =3D ixgbevf_dev_rss_reta_update, > > + .reta_query =3D ixgbevf_dev_rss_reta_query, > > .rss_hash_update =3D ixgbevf_dev_rss_hash_update, > > .rss_hash_conf_get =3D ixgbevf_dev_rss_hash_conf_get, > > }; > > @@ -5557,6 +5566,100 @@ ixgbe_set_eeprom(struct rte_eth_dev *dev, > > return eeprom->ops.write_buffer(hw, first, length, data); } > > > > +static int > > +ixgbevf_dev_rss_reta_update(struct rte_eth_dev *dev, > > + struct rte_eth_rss_reta_entry64 *reta_conf, > > + uint16_t reta_size) > > +{ > > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > > + uint32_t reta, r; > > + uint16_t i, j; > > + uint16_t idx, shift; > > + uint8_t mask; > > + > > + if (hw->mac.type !=3D ixgbe_mac_X550_vf && > > + hw->mac.type !=3D ixgbe_mac_X550EM_x_vf) { > > + PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " > > + "VF NIC."); > > + return -ENOTSUP; > > + } > > + > > + if (reta_size !=3D ETH_RSS_RETA_SIZE_64) { > > + PMD_DRV_LOG(ERR, "The size of hash lookup table configured > " > > + "(%d) doesn't match the number of hardware can " > > + "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64); > > + return -EINVAL; > > + } > > + > > + for (i =3D 0; i < reta_size; i +=3D IXGBE_4_BIT_WIDTH) { > > + idx =3D i / RTE_RETA_GROUP_SIZE; > > + shift =3D i % RTE_RETA_GROUP_SIZE; > > + mask =3D (uint8_t)((reta_conf[idx].mask >> shift) & > > + IXGBE_4_BIT_WIDTH); > > + if (!mask) > > + continue; > > + if (mask =3D=3D IXGBE_4_BIT_WIDTH) > > + r =3D 0; > > + else > > + r =3D IXGBE_READ_REG(hw, IXGBE_VFRETA(i >> 2)); > > + > > + for (j =3D 0, reta =3D 0; j < IXGBE_4_BIT_WIDTH; j++) { > > + if (mask & (0x1 << j)) > > + reta |=3D reta_conf[idx].reta[shift + j] << > > + (CHAR_BIT * j); > > + else > > + reta |=3D r & > > + (IXGBE_8_BIT_MASK << (CHAR_BIT * j)); > > + } > > + IXGBE_WRITE_REG(hw, IXGBE_VFRETA(i >> 2), reta); > > + } > > + > > + return 0; > > +} > > + > > +static int > > +ixgbevf_dev_rss_reta_query(struct rte_eth_dev *dev, > > + struct rte_eth_rss_reta_entry64 *reta_conf, > > + uint16_t reta_size) > > +{ > > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > > + uint32_t reta; > > + uint16_t i, j; > > + uint16_t idx, shift; > > + uint8_t mask; > > + > > + if (hw->mac.type !=3D ixgbe_mac_X550_vf && > > + hw->mac.type !=3D ixgbe_mac_X550EM_x_vf) { > > + return ixgbe_dev_rss_reta_query(dev, reta_conf, reta_size); > > + } > > + > > + if (reta_size !=3D ETH_RSS_RETA_SIZE_64) { > > + PMD_DRV_LOG(ERR, "The size of hash lookup table configured > " > > + "(%d) doesn't match the number of hardware can " > > + "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64); > > + return -EINVAL; > > + } > > + > > + for (i =3D 0; i < reta_size; i +=3D IXGBE_4_BIT_WIDTH) { > > + idx =3D i / RTE_RETA_GROUP_SIZE; > > + shift =3D i % RTE_RETA_GROUP_SIZE; > > + mask =3D (uint8_t)((reta_conf[idx].mask >> shift) & > > + IXGBE_4_BIT_MASK); > > + if (!mask) > > + continue; > > + > > + reta =3D IXGBE_READ_REG(hw, IXGBE_VFRETA(i >> 2)); > > + for (j =3D 0; j < IXGBE_4_BIT_WIDTH; j++) { > > + if (mask & (0x1 << j)) > > + reta_conf[idx].reta[shift + j] =3D > > + ((reta >> (CHAR_BIT * j)) & > > + IXGBE_8_BIT_MASK); > > + } > > + } > > + > > + return 0; > > +} > > + >=20 > Same as for other 3 patches in that series: >90% of the code is just copy= & paste > of existing one, with different HW registers name and reta_size. > Pls unify. > Konstantin Thanks. I'll try to condense the code. And the same for the other 3 patches= . >=20 > > static struct rte_driver rte_ixgbe_driver =3D { > > .type =3D PMD_PDEV, > > .init =3D rte_ixgbe_pmd_init, > > -- > > 1.9.3