From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id B34EDD1B2 for ; Tue, 28 Mar 2017 10:45:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490690744; x=1522226744; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=jpSyF7SHWeBOyi0dz1sXbw6Fl6r5mksA3bpIEPFGWPw=; b=FU4QmJCC0igNMAY5mSJstftg7AmNiGNiQfSt0fmu4JmZcTtsgDk6nNP0 0zYxsVPerG0bcVLsoMt9KROHWL16aA==; Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Mar 2017 01:45:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,236,1486454400"; d="scan'208";a="71215371" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga004.jf.intel.com with ESMTP; 28 Mar 2017 01:45:40 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 28 Mar 2017 01:45:40 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 28 Mar 2017 01:45:40 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.212]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.224]) with mapi id 14.03.0248.002; Tue, 28 Mar 2017 16:45:38 +0800 From: "Lu, Wenzhuo" To: "Iremonger, Bernard" , "dev@dpdk.org" , "Xing, Beilei" , "Wu, Jingjing" CC: "Zhang, Helin" , "Iremonger, Bernard" Thread-Topic: [dpdk-dev] [PATCH v2 2/3] net/i40e: parse QinQ pattern Thread-Index: AQHSo/QP8hmheHdcdEWLtwxywWUDRqGp9qMQ Date: Tue, 28 Mar 2017 08:45:37 +0000 Message-ID: <6A0DE07E22DDAD4C9103DF62FEBC09093B583943@shsmsx102.ccr.corp.intel.com> References: <1488552491-20432-1-git-send-email-bernard.iremonger@intel.com> <1490287113-8895-3-git-send-email-bernard.iremonger@intel.com> In-Reply-To: <1490287113-8895-3-git-send-email-bernard.iremonger@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 2/3] net/i40e: parse QinQ pattern X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Mar 2017 08:45:44 -0000 Hi Bernard, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bernard Iremonger > Sent: Friday, March 24, 2017 12:39 AM > To: dev@dpdk.org; Xing, Beilei; Wu, Jingjing > Cc: Zhang, Helin; Iremonger, Bernard > Subject: [dpdk-dev] [PATCH v2 2/3] net/i40e: parse QinQ pattern >=20 > add QinQ pattern. > add i40e_flow_parse_qinq_pattern function. > add i40e_flow_parse_qinq_filter function. >=20 > Signed-off-by: Bernard Iremonger > --- > drivers/net/i40e/i40e_flow.c | 194 > ++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 192 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c = index > 8d7765a..e53ab22 100644 > --- a/drivers/net/i40e/i40e_flow.c > +++ b/drivers/net/i40e/i40e_flow.c > +/* Pattern matched QINQ */ > +static enum rte_flow_item_type pattern_qinq_1[] =3D { > + RTE_FLOW_ITEM_TYPE_ETH, > + RTE_FLOW_ITEM_TYPE_VLAN, > + RTE_FLOW_ITEM_TYPE_VLAN, > + RTE_FLOW_ITEM_TYPE_END, > +}; > + > + /* Check specification and mask to get the filter type */ > + if (vlan_spec && vlan_mask && > + (vlan_mask->tci =3D=3D rte_cpu_to_be_16(I40E_TCI_MASK))) { > + /* If there's inner vlan */ > + if (vlan_flag) I think vlan_flag here is always 0, according to defined 'pattern_qinq_1'. = Single vlan is not supported. > + filter->inner_vlan =3D rte_be_to_cpu_16(o_vlan_spec- > >tci) > + & I40E_TCI_MASK; > + else { > + /* There is an inner and outer vlan */ > + filter->outer_vlan =3D rte_be_to_cpu_16(o_vlan_spec- > >tci) > + & I40E_TCI_MASK; > + filter->inner_vlan =3D rte_be_to_cpu_16(i_vlan_spec- > >tci) > + & I40E_TCI_MASK; > + }