From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 8BE32DE0 for ; Mon, 13 Jul 2015 11:01:13 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 13 Jul 2015 02:01:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,461,1432623600"; d="scan'208";a="761335591" Received: from kmsmsx152.gar.corp.intel.com ([172.21.73.87]) by fmsmga002.fm.intel.com with ESMTP; 13 Jul 2015 02:01:09 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.110.14) by KMSMSX152.gar.corp.intel.com (172.21.73.87) with Microsoft SMTP Server (TLS) id 14.3.224.2; Mon, 13 Jul 2015 17:00:50 +0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.165]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.46]) with mapi id 14.03.0224.002; Mon, 13 Jul 2015 17:00:43 +0800 From: "Lu, Wenzhuo" To: motomu , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] drivers/net/e1000/igb_ethdev.c:fix eth_igb_add_del_flex_filter Thread-Index: AQHQlfH2WGyoDjTRuUOi8jT02YVEb53ZZ/0g Date: Mon, 13 Jul 2015 09:00:42 +0000 Message-ID: <6A0DE07E22DDAD4C9103DF62FEBC0909CF99FA@shsmsx102.ccr.corp.intel.com> References: <1432484252-3517-1-git-send-email-motomu@hongo.wide.ad.jp> In-Reply-To: <1432484252-3517-1-git-send-email-motomu@hongo.wide.ad.jp> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] drivers/net/e1000/igb_ethdev.c:fix eth_igb_add_del_flex_filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Jul 2015 09:01:14 -0000 Hi Motomu, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of motomu > Sent: Monday, May 25, 2015 12:18 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] drivers/net/e1000/igb_ethdev.c:fix > eth_igb_add_del_flex_filter >=20 > From: Motomu Utsumi >=20 > in add flexfiler it always write to same register address, so when try to= adapt > some filters only last one is enabled. I don't understand what the " same register address " means. So, I don't th= ink it's necessary to change the code. Would you like to give more details?= Thanks. Wenzhuo > I substitute value based on based on flex_filter->index for reg_off. >=20 > in del flexfilter, it delete target filter and also delete first filter b= ecause of similar > reason. > I substitute value based on based on it->index for reg_off. >=20 > --- > drivers/net/e1000/igb_ethdev.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethde= v.c > index e4b370d..5a7f50a 100644 > --- a/drivers/net/e1000/igb_ethdev.c > +++ b/drivers/net/e1000/igb_ethdev.c > @@ -2781,10 +2781,6 @@ eth_igb_add_del_flex_filter(struct rte_eth_dev *de= v, > } >=20 > wufc =3D E1000_READ_REG(hw, E1000_WUFC); > - if (flex_filter->index < E1000_MAX_FHFT) > - reg_off =3D E1000_FHFT(flex_filter->index); > - else > - reg_off =3D E1000_FHFT_EXT(flex_filter->index - > E1000_MAX_FHFT); >=20 > if (add) { > if (eth_igb_flex_filter_lookup(&filter_info->flex_list, > @@ -2813,6 +2809,10 @@ eth_igb_add_del_flex_filter(struct rte_eth_dev *de= v, > rte_free(flex_filter); > return -ENOSYS; > } > + if (flex_filter->index < E1000_MAX_FHFT) > + reg_off =3D E1000_FHFT(flex_filter->index); > + else > + reg_off =3D E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT); >=20 > E1000_WRITE_REG(hw, E1000_WUFC, wufc | > E1000_WUFC_FLEX_HQ | > (E1000_WUFC_FLX0 << flex_filter->index)); > @@ -2841,6 +2841,10 @@ eth_igb_add_del_flex_filter(struct rte_eth_dev *de= v, > rte_free(flex_filter); > return -ENOENT; > } > + if (it->index < E1000_MAX_FHFT) > + reg_off =3D E1000_FHFT(it->index); > + else > + reg_off =3D E1000_FHFT_EXT(it->index - E1000_MAX_FHFT); >=20 > for (i =3D 0; i < E1000_FHFT_SIZE_IN_DWD; i++) > E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0); > -- > 1.8.3.1