From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50040.outbound.protection.outlook.com [40.107.5.40]) by dpdk.org (Postfix) with ESMTP id D73F31B272 for ; Wed, 10 Apr 2019 19:37:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IqT0VN2b7A7DT9jzam9m/JT3NibyTNumHREA3o0IjI4=; b=J7yCYSBM0c2RUV0KL9/nn1X3b/nAKZ8pMhLrvdeL3V2a05RZnE/4hSMtdkq6sJ8I/UFvSeTNS0tW3sPh1uwrRIZtrDb/7Muqby6zP55oEKvjkz7T/TWIdtaIPRHHLm3A8HWIyalm+HsiePnbrl1KW54IsMRQHgQO6w+b+7tjTsA= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3946.eurprd05.prod.outlook.com (52.134.71.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.15; Wed, 10 Apr 2019 17:37:46 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Wed, 10 Apr 2019 17:37:46 +0000 From: Yongseok Koh To: Pavan Nikhilesh CC: Thomas Monjalon , dev , Jerin Jacob , "jerinjacobk@gmail.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y1qMWA Date: Wed, 10 Apr 2019 17:37:45 +0000 Message-ID: <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> In-Reply-To: <20190410161400.9361-2-jerinj@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fb4beb00-ec22-4afa-1302-08d6bddb3e5a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:DB3PR0502MB3946; x-ms-traffictypediagnostic: DB3PR0502MB3946: x-ld-processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtAddr x-microsoft-antispam-prvs: x-forefront-prvs: 00032065B2 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(346002)(376002)(136003)(39860400002)(396003)(189003)(199004)(2616005)(105586002)(25786009)(68736007)(106356001)(5660300002)(8676002)(81166006)(229853002)(8936002)(33656002)(11346002)(6916009)(446003)(81156014)(3846002)(476003)(486006)(6116002)(76176011)(99286004)(6512007)(26005)(2906002)(102836004)(53546011)(6506007)(186003)(66066001)(53936002)(6246003)(316002)(14454004)(83716004)(54906003)(97736004)(478600001)(7736002)(305945005)(36756003)(6436002)(6486002)(86362001)(71190400001)(71200400001)(256004)(4326008)(82746002); DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3946; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XhMoY+jdL1Wrf57K+BrCx6jDGRjGWfXR8D2oXKtlXdfxmkeC+pbKFKOkvuGztfnA8Bw4lDX8s+0e72eMNTe2mvCW0+a2ENz/1VWAnTUY3k8JFoDE1941Fy9UyzlDB17sZqmeo7CUl26mR1TTxTCvJWdB7iqnRK6LfGyIiO478/uRoi135TlTtRj1allWzJEKJ4/SsAiImxkTBOf4aU56vlfRWb16N/oEApqJ2UGtxxp+pslt+zDGfwyGfUMwP53CcsbBR1iNhq474eBlT5HKhC8PjJW8J2OH/aqnkakyIjNkNpRetxr2sDNBpx2xmjIKAxYuukoIW/4zyuRRJWrp6ICvg8IXUBRdB2/P0YsVj6nkRWxP4IFzFR3X/gbmExy6RptrRVEHav1KIdTYFDd/3iOXdBybyxN32TrrhYD9uNI= Content-Type: text/plain; charset="us-ascii" Content-ID: <8FA61E3F82FCB345BF9E27D6D56ED07A@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: fb4beb00-ec22-4afa-1302-08d6bddb3e5a X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 17:37:45.9921 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3946 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Apr 2019 17:37:48 -0000 > On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >=20 > From: Pavan Nikhilesh >=20 > Currently, RTE_* flags are set based on the implementer ID but there migh= t > be some micro arch specific differences from the same vendor > eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >=20 > Signed-off-by: Pavan Nikhilesh > Signed-off-by: Jerin Jacob > --- > config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ > 1 file changed, 32 insertions(+), 24 deletions(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 170a4981a..24bce2b39 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >=20 > arm_force_native_march =3D false >=20 > -machine_args_generic =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto']], > - ['native', ['-march=3Dnative']], > - ['0xd03', ['-mcpu=3Dcortex-a53']], > - ['0xd04', ['-mcpu=3Dcortex-a35']], > - ['0xd05', ['-mcpu=3Dcortex-a55']], > - ['0xd07', ['-mcpu=3Dcortex-a57']], > - ['0xd08', ['-mcpu=3Dcortex-a72']], > - ['0xd09', ['-mcpu=3Dcortex-a73']], > - ['0xd0a', ['-mcpu=3Dcortex-a75']], > - ['0xd0b', ['-mcpu=3Dcortex-a76']], > -] > -machine_args_cavium =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > - ['native', ['-march=3Dnative']], > - ['0xa1', ['-mcpu=3Dthunderxt88']], > - ['0xa2', ['-mcpu=3Dthunderxt81']], > - ['0xa3', ['-mcpu=3Dthunderxt83']]] > - > flags_common_default =3D [ > # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) > # to determine the best threshold in code. Refer to notes in source file > @@ -52,12 +33,10 @@ flags_generic =3D [ > ['RTE_USE_C11_MEM_MODEL', true], > ['RTE_CACHE_LINE_SIZE', 128]] > flags_cavium =3D [ > - ['RTE_MACHINE', '"thunderx"'], > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 96], > - ['RTE_MAX_VFIO_GROUPS', 128], > - ['RTE_USE_C11_MEM_MODEL', false]] > + ['RTE_MAX_VFIO_GROUPS', 128]] > flags_dpaa =3D [ > ['RTE_MACHINE', '"dpaa"'], > ['RTE_USE_C11_MEM_MODEL', true], > @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ > ['RTE_MAX_NUMA_NODES', 1], > ['RTE_MAX_LCORE', 16], > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > +flags_default_extra =3D [] > +flags_thunderx_extra =3D [ > + ['RTE_MACHINE', '"thunderx"'], > + ['RTE_USE_C11_MEM_MODEL', false]] > + > +machine_args_generic =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto']], > + ['native', ['-march=3Dnative']], > + ['0xd03', ['-mcpu=3Dcortex-a53']], > + ['0xd04', ['-mcpu=3Dcortex-a35']], > + ['0xd07', ['-mcpu=3Dcortex-a57']], > + ['0xd08', ['-mcpu=3Dcortex-a72']], > + ['0xd09', ['-mcpu=3Dcortex-a73']], > + ['0xd0a', ['-mcpu=3Dcortex-a75']]] > + > +machine_args_cavium =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > + ['native', ['-march=3Dnative']], > + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] > @@ -157,8 +157,16 @@ else > endif > foreach marg: machine[2] > if marg[0] =3D=3D impl_pn > - foreach f: marg[1] > - machine_args +=3D f > + foreach flag: marg[1] > + if cc.has_argument(flag) > + machine_args +=3D flag > + endif > + endforeach > + # Apply any extra machine specific flags. > + foreach flag: marg.get(2, flags_default_extra) > + if flag.length() > 0 > + dpdk_conf.set(flag[0], flag[1]) > + endif Let me continue the discussion from v7 here. Seems I wan't clear enough. Let me take an example. If the host is thunderx2 (0xaf) and compiler is old= er than v7, flags_thunderx2_extra isn't set. This means, for example, RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might w= ant to set it regardless of gcc version. You could skip setting -mcpu with sett= ing the extra flags. Thoughts? Thanks, Yongseok From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id B9994A0096 for ; Wed, 10 Apr 2019 19:37:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 192921B274; Wed, 10 Apr 2019 19:37:50 +0200 (CEST) Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50040.outbound.protection.outlook.com [40.107.5.40]) by dpdk.org (Postfix) with ESMTP id D73F31B272 for ; Wed, 10 Apr 2019 19:37:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IqT0VN2b7A7DT9jzam9m/JT3NibyTNumHREA3o0IjI4=; b=J7yCYSBM0c2RUV0KL9/nn1X3b/nAKZ8pMhLrvdeL3V2a05RZnE/4hSMtdkq6sJ8I/UFvSeTNS0tW3sPh1uwrRIZtrDb/7Muqby6zP55oEKvjkz7T/TWIdtaIPRHHLm3A8HWIyalm+HsiePnbrl1KW54IsMRQHgQO6w+b+7tjTsA= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3946.eurprd05.prod.outlook.com (52.134.71.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.15; Wed, 10 Apr 2019 17:37:46 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Wed, 10 Apr 2019 17:37:46 +0000 From: Yongseok Koh To: Pavan Nikhilesh CC: Thomas Monjalon , dev , Jerin Jacob , "jerinjacobk@gmail.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y1qMWA Date: Wed, 10 Apr 2019 17:37:45 +0000 Message-ID: <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> In-Reply-To: <20190410161400.9361-2-jerinj@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fb4beb00-ec22-4afa-1302-08d6bddb3e5a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XhMoY+jdL1Wrf57K+BrCx6jDGRjGWfXR8D2oXKtlXdfxmkeC+pbKFKOkvuGztfnA8Bw4lDX8s+0e72eMNTe2mvCW0+a2ENz/1VWAnTUY3k8JFoDE1941Fy9UyzlDB17sZqmeo7CUl26mR1TTxTCvJWdB7iqnRK6LfGyIiO478/uRoi135TlTtRj1allWzJEKJ4/SsAiImxkTBOf4aU56vlfRWb16N/oEApqJ2UGtxxp+pslt+zDGfwyGfUMwP53CcsbBR1iNhq474eBlT5HKhC8PjJW8J2OH/aqnkakyIjNkNpRetxr2sDNBpx2xmjIKAxYuukoIW/4zyuRRJWrp6ICvg8IXUBRdB2/P0YsVj6nkRWxP4IFzFR3X/gbmExy6RptrRVEHav1KIdTYFDd/3iOXdBybyxN32TrrhYD9uNI= Content-Type: text/plain; charset="UTF-8" Content-ID: <8FA61E3F82FCB345BF9E27D6D56ED07A@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: fb4beb00-ec22-4afa-1302-08d6bddb3e5a X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 17:37:45.9921 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3946 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190410173745.WdRsxWh0RWSsc_6sbubk7x3d_T8T2AaEbs0BYY57mk8@z> > On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >=20 > From: Pavan Nikhilesh >=20 > Currently, RTE_* flags are set based on the implementer ID but there migh= t > be some micro arch specific differences from the same vendor > eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >=20 > Signed-off-by: Pavan Nikhilesh > Signed-off-by: Jerin Jacob > --- > config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ > 1 file changed, 32 insertions(+), 24 deletions(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 170a4981a..24bce2b39 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >=20 > arm_force_native_march =3D false >=20 > -machine_args_generic =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto']], > - ['native', ['-march=3Dnative']], > - ['0xd03', ['-mcpu=3Dcortex-a53']], > - ['0xd04', ['-mcpu=3Dcortex-a35']], > - ['0xd05', ['-mcpu=3Dcortex-a55']], > - ['0xd07', ['-mcpu=3Dcortex-a57']], > - ['0xd08', ['-mcpu=3Dcortex-a72']], > - ['0xd09', ['-mcpu=3Dcortex-a73']], > - ['0xd0a', ['-mcpu=3Dcortex-a75']], > - ['0xd0b', ['-mcpu=3Dcortex-a76']], > -] > -machine_args_cavium =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > - ['native', ['-march=3Dnative']], > - ['0xa1', ['-mcpu=3Dthunderxt88']], > - ['0xa2', ['-mcpu=3Dthunderxt81']], > - ['0xa3', ['-mcpu=3Dthunderxt83']]] > - > flags_common_default =3D [ > # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) > # to determine the best threshold in code. Refer to notes in source file > @@ -52,12 +33,10 @@ flags_generic =3D [ > ['RTE_USE_C11_MEM_MODEL', true], > ['RTE_CACHE_LINE_SIZE', 128]] > flags_cavium =3D [ > - ['RTE_MACHINE', '"thunderx"'], > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 96], > - ['RTE_MAX_VFIO_GROUPS', 128], > - ['RTE_USE_C11_MEM_MODEL', false]] > + ['RTE_MAX_VFIO_GROUPS', 128]] > flags_dpaa =3D [ > ['RTE_MACHINE', '"dpaa"'], > ['RTE_USE_C11_MEM_MODEL', true], > @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ > ['RTE_MAX_NUMA_NODES', 1], > ['RTE_MAX_LCORE', 16], > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > +flags_default_extra =3D [] > +flags_thunderx_extra =3D [ > + ['RTE_MACHINE', '"thunderx"'], > + ['RTE_USE_C11_MEM_MODEL', false]] > + > +machine_args_generic =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto']], > + ['native', ['-march=3Dnative']], > + ['0xd03', ['-mcpu=3Dcortex-a53']], > + ['0xd04', ['-mcpu=3Dcortex-a35']], > + ['0xd07', ['-mcpu=3Dcortex-a57']], > + ['0xd08', ['-mcpu=3Dcortex-a72']], > + ['0xd09', ['-mcpu=3Dcortex-a73']], > + ['0xd0a', ['-mcpu=3Dcortex-a75']]] > + > +machine_args_cavium =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > + ['native', ['-march=3Dnative']], > + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] > @@ -157,8 +157,16 @@ else > endif > foreach marg: machine[2] > if marg[0] =3D=3D impl_pn > - foreach f: marg[1] > - machine_args +=3D f > + foreach flag: marg[1] > + if cc.has_argument(flag) > + machine_args +=3D flag > + endif > + endforeach > + # Apply any extra machine specific flags. > + foreach flag: marg.get(2, flags_default_extra) > + if flag.length() > 0 > + dpdk_conf.set(flag[0], flag[1]) > + endif Let me continue the discussion from v7 here. Seems I wan't clear enough. Let me take an example. If the host is thunderx2 (0xaf) and compiler is old= er than v7, flags_thunderx2_extra isn't set. This means, for example, RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might w= ant to set it regardless of gcc version. You could skip setting -mcpu with sett= ing the extra flags. Thoughts? Thanks, Yongseok