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* [dpdk-dev] [PATCH 00/14] ice: base code update
@ 2021-03-02  7:23 Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support Qi Zhang
                   ` (14 more replies)
  0 siblings, 15 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang

Main change:
1. Support GTPU inner l3/l4 for FDIR
2. Support GTPU extention header for FDIR
3. Support switch filter (GTPU tunnel + IP flow)
4. couple bug fixes.

Qi Zhang (14):
  net/ice/base: add firmware log support
  net/ice/base: signed external device package programming
  net/ice/base: post update double reset solution restriction
  net/ice/base: enable GTPU inner L3/L4 for FDIR
  net/ice/base: expose link configuration error
  net/ice/base: enable more GTPU inner L3 fields for FDIR
  net/ice/base: support for switch filter (GTP tunnel+IP flow)
  net/ice/base: support GTPU IP inner IPv6 for FDIR
  net/ice/base: fix incorrect payload indicator on PTYPE
  net/ice/base: mark PTYPE 2 as reserved
  net/ice/base: add code to update boost TCAM for DVM
  net/ice/base: update GTPU EH dummy pkts for FDIR
  net/ice/base: fix uninitialized struct
  net/ice/base: cleanup fltr list in case of allocation issues

 drivers/net/ice/base/ice_adminq_cmd.h    |  83 ++++-
 drivers/net/ice/base/ice_common.c        |   1 +
 drivers/net/ice/base/ice_fdir.c          | 412 ++++++++++++++++-------
 drivers/net/ice/base/ice_fdir.h          |  22 ++
 drivers/net/ice/base/ice_flex_pipe.c     | 223 ++++++++++--
 drivers/net/ice/base/ice_flex_pipe.h     |   1 +
 drivers/net/ice/base/ice_flex_type.h     |  13 +
 drivers/net/ice/base/ice_flow.c          |   9 +-
 drivers/net/ice/base/ice_lan_tx_rx.h     |   4 +-
 drivers/net/ice/base/ice_protocol_type.h |   8 +-
 drivers/net/ice/base/ice_switch.c        | 117 ++++---
 drivers/net/ice/base/ice_type.h          |   6 +
 drivers/net/ice/base/ice_vlan_mode.c     |   7 +
 13 files changed, 679 insertions(+), 227 deletions(-)

-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 02/14] net/ice/base: signed external device package programming Qi Zhang
                   ` (13 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Amir Shay

Currently we do not provide full end-to-end solution for system level
debug and diagnostics. This change purpose is to fulfill design and
implementation gaps to provide full end-to-end (HW-FW-SW) diagnostic
solution. In addition to functional improvements, it will provide
feasible, user-friendly Debug information.

Signed-off-by: Amir Shay <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_adminq_cmd.h | 54 ++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 8f72f0db33..a345fb5a61 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2730,6 +2730,50 @@ struct ice_aqc_clear_health_status {
 	__le32 reserved[4];
 };
 
+/* Set FW Logging configuration (indirect 0xFF30)
+ * Register for FW Logging (indirect 0xFF31)
+ * Query FW Logging (indirect 0xFF32)
+ * FW Log Event (indirect 0xFF33)
+ * Get FW Log (indirect 0xFF34)
+ * Clear FW Log (indirect 0xFF35)
+ */
+
+struct ice_aqc_fw_log {
+	u8 cmd_flags;
+#define ICE_AQC_FW_LOG_CONF_UART_EN	BIT(0)
+#define ICE_AQC_FW_LOG_CONF_AQ_EN	BIT(1)
+#define ICE_AQC_FW_LOG_CONF_SET_VALID	BIT(3)
+#define ICE_AQC_FW_LOG_AQ_REGISTER	BIT(0)
+#define ICE_AQC_FW_LOG_AQ_QUERY		BIT(2)
+#define ICE_AQC_FW_LOG_PERSISTENT	BIT(0)
+	u8 rsp_flag;
+#define ICE_AQC_FW_LOG_MORE_DATA	BIT(1)
+	__le16 fw_rt_msb;
+	union {
+		struct {
+			__le32 fw_rt_lsb;
+		} sync;
+		struct {
+			__le16 log_resolution;
+#define ICE_AQC_FW_LOG_MIN_RESOLUTION		(1)
+#define ICE_AQC_FW_LOG_MAX_RESOLUTION		(128)
+			__le16 mdl_cnt;
+		} cfg;
+	} ops;
+	__le32 addr_high;
+	__le32 addr_low;
+};
+
+/* Response Buffer for:
+ *    Set Firmware Logging Configuration (0xFF30)
+ *    Query FW Logging (0xFF32)
+ */
+struct ice_aqc_fw_log_cfg_resp {
+	__le16 module_identifier;
+	u8 log_level;
+	u8 rsvd0;
+};
+
 /**
  * struct ice_aq_desc - Admin Queue (AQ) descriptor
  * @flags: ICE_AQ_FLAG_* flags
@@ -3090,7 +3134,15 @@ enum ice_adminq_opc {
 	ice_aqc_opc_set_health_status_config		= 0xFF20,
 	ice_aqc_opc_get_supported_health_status_codes	= 0xFF21,
 	ice_aqc_opc_get_health_status			= 0xFF22,
-	ice_aqc_opc_clear_health_status			= 0xFF23
+	ice_aqc_opc_clear_health_status			= 0xFF23,
+
+	/* FW Logging Commands */
+	ice_aqc_opc_fw_logs_config			= 0xFF30,
+	ice_aqc_opc_fw_logs_register			= 0xFF31,
+	ice_aqc_opc_fw_logs_query			= 0xFF32,
+	ice_aqc_opc_fw_logs_event			= 0xFF33,
+	ice_aqc_opc_fw_logs_get				= 0xFF34,
+	ice_aqc_opc_fw_logs_clear			= 0xFF35
 };
 
 #endif /* _ICE_ADMINQ_CMD_H_ */
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 02/14] net/ice/base: signed external device package programming
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction Qi Zhang
                   ` (12 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Amir Shay

External topology devices (e.g. PHYs) connected to Columbiaville or to
SoC that includes CPK IP might have a firmware engine within the device
and the firmware is usually loaded from NVM connected to the topology
device.
In some cases, those firmware packages might need to be regularly
updated in a secure way to prevent malicious user to burn malicious
firmware into the topology device. In other cases, the topology device
firmware might be burned independently, as burning the NVM attached to
the device might cause the device to stop function but could be fixed
without permanent damage.
SoC topologies also enable mezzanine card, with an ID EEPROM
within it. This ID EEPROM might need an update also.
This patch provides these abilities.

Signed-off-by: Amir Shay <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_adminq_cmd.h | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index a345fb5a61..3f2b4cd54b 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1506,11 +1506,12 @@ struct ice_aqc_get_link_status_data {
 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA	BIT(6)
 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA	BIT(7)
 	u8 link_cfg_err;
-#define ICE_AQ_LINK_CFG_ERR		BIT(0)
-#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL	BIT(2)
+#define ICE_AQ_LINK_CFG_ERR			BIT(0)
+#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL		BIT(2)
 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL	BIT(3)
 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR	BIT(4)
 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED	BIT(5)
+#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE	BIT(6)
 	u8 link_info;
 #define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
 #define ICE_AQ_LINK_FAULT		BIT(1)
@@ -1716,6 +1717,25 @@ struct ice_aqc_sw_gpio {
 	u8 rsvd[12];
 };
 
+/* Program topology device NVM (direct, 0x06F2) */
+struct ice_aqc_program_topology_device_nvm {
+	u8 lport_num;
+	u8 lport_num_valid;
+	u8 node_type_ctx;
+	u8 index;
+	u8 rsvd[12];
+};
+
+/* Read topology device NVM (indirect, 0x06F3) */
+struct ice_aqc_read_topology_device_nvm {
+	u8 lport_num;
+	u8 lport_num_valid;
+	u8 node_type_ctx;
+	u8 index;
+	__le32 start_address;
+	u8 data_read[8];
+};
+
 /* NVM Read command (indirect 0x0701)
  * NVM Erase commands (direct 0x0702)
  * NVM Write commands (indirect 0x0703)
@@ -3059,6 +3079,8 @@ enum ice_adminq_opc {
 	ice_aqc_opc_sff_eeprom				= 0x06EE,
 	ice_aqc_opc_sw_set_gpio				= 0x06EF,
 	ice_aqc_opc_sw_get_gpio				= 0x06F0,
+	ice_aqc_opc_program_topology_device_nvm		= 0x06F2,
+	ice_aqc_opc_read_topology_device_nvm		= 0x06F3,
 
 	/* NVM commands */
 	ice_aqc_opc_nvm_read				= 0x0701,
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 02/14] net/ice/base: signed external device package programming Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 04/14] net/ice/base: enable GTPU inner L3/L4 for FDIR Qi Zhang
                   ` (11 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Amir Shay

Add capability which indicates double reset solution restriction.
Added "Post-update EMPR enabled" field to "Response Flags" field
(byte 19 in the response structure).

Signed-off-by: Amir Shay <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_adminq_cmd.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 3f2b4cd54b..a31c27a633 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -111,6 +111,7 @@ struct ice_aqc_list_caps_elem {
 #define ICE_AQC_CAPS_MAX_MTU				0x0047
 #define ICE_AQC_CAPS_IWARP				0x0051
 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076
+#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077
 #define ICE_AQC_CAPS_NVM_MGMT				0x0080
 
 	u8 major_ver;
@@ -1765,6 +1766,7 @@ struct ice_aqc_nvm {
 #define ICE_AQC_NVM_POR_FLAG	0	/* Used by NVM Write completion on ARQ */
 #define ICE_AQC_NVM_PERST_FLAG	1
 #define ICE_AQC_NVM_EMPR_FLAG	2
+#define ICE_AQC_NVM_EMPR_ENA		BIT(0)
 	__le16 module_typeid;
 	__le16 length;
 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 04/14] net/ice/base: enable GTPU inner L3/L4 for FDIR
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (2 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 05/14] net/ice/base: expose link configuration error Qi Zhang
                   ` (10 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang

For FDIR, GTPU with inner L3/L4 layers should only support inner
L3/L4 addrs/ports, instead of outer fields. Thus, we use TUN offsets
for GTPU IP/EH to insert inner L3/L4 addrs/ports fields.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_fdir.c | 122 +++++++++++++++++++++++---------
 drivers/net/ice/base/ice_fdir.h |  10 +++
 2 files changed, 97 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 500b081e54..2c479dfbd4 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -72,32 +72,29 @@ static const u8 ice_fdir_ipv4_gtpu4_pkt[] = {
 static const u8 ice_fdir_udp4_gtpu4_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x4c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00,
-	0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00,
+	0x00, 0x40, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2c,
+	0x00, 0x6f, 0x30, 0xff, 0x00, 0x1c, 0x00, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x1c, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x11, 0x3a, 0x24, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x08, 0xbe, 0xc7, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_tcp4_gtpu4_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x58, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00,
-	0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x28, 0x00, 0x00, 0x40, 0x00, 0x40, 0x06,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
+	0x00, 0x4c, 0x30, 0xff, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x28, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x06, 0x3a, 0x23, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x4e, 0xd2,
+	0x00, 0x00, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_ipv4_gtpu4_eh_pkt[] = {
@@ -1387,19 +1384,44 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 			   ice_fdir_pkt[idx].pkt_len, ICE_NONDMA_TO_NONDMA);
 		loc = pkt;
 	} else {
-		enum ice_status ret;
-
-		ret = ice_fdir_get_open_tunnel_port(hw, flow, &tnl_port);
-		if (ret)
-			return ret;
-
 		if (!ice_fdir_pkt[idx].tun_pkt)
 			return ICE_ERR_PARAM;
-		ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
-			   ice_fdir_pkt[idx].tun_pkt_len, ICE_NONDMA_TO_NONDMA);
-		ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_DST_PORT_OFFSET,
-				   HTONS(tnl_port));
-		loc = &pkt[ICE_FDIR_TUN_PKT_OFF];
+
+		switch (flow) {
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
+			ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+				   ice_fdir_pkt[idx].tun_pkt_len,
+				   ICE_NONDMA_TO_NONDMA);
+			loc = &pkt[ICE_FDIR_GTPU_IP_INNER_PKT_OFF];
+			break;
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP:
+			ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+				   ice_fdir_pkt[idx].tun_pkt_len,
+				   ICE_NONDMA_TO_NONDMA);
+			loc = &pkt[ICE_FDIR_GTPU_EH_INNER_PKT_OFF];
+			break;
+		default:
+			if (ice_fdir_get_open_tunnel_port(hw, flow, &tnl_port))
+				return ICE_ERR_DOES_NOT_EXIST;
+
+			ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
+				   ice_fdir_pkt[idx].tun_pkt_len,
+				   ICE_NONDMA_TO_NONDMA);
+			ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_DST_PORT_OFFSET,
+					   HTONS(tnl_port));
+			loc = &pkt[ICE_FDIR_TUN_PKT_OFF];
+			break;
+		}
 	}
 
 	/* Reverse the src and dst, since the HW expects them to be from Tx
@@ -1491,7 +1513,6 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 		ice_pkt_insert_mac_addr(loc + ETH_ALEN, input->ext_data.src_mac);
 		break;
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU:
-	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER:
 		ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
 				   input->ip.v4.src_ip);
 		ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
@@ -1499,13 +1520,18 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 		ice_pkt_insert_u32(loc, ICE_IPV4_GTPU_TEID_OFFSET,
 				   input->gtpu_data.teid);
 		break;
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4:
+		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
+				   input->ip.v4.src_ip);
+		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
+				   input->ip.v4.dst_ip);
+		break;
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH:
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW:
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP:
-	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:
-	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
-	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP:
-	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER:
 		ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
 				   input->ip.v4.src_ip);
 		ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
@@ -1515,6 +1541,32 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 		ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET,
 				      input->gtpu_data.qfi);
 		break;
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP:
+		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
+				   input->ip.v4.src_ip);
+		ice_pkt_insert_u16(loc, ICE_UDP4_NO_MAC_DST_PORT_OFFSET,
+				   input->ip.v4.src_port);
+		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
+				   input->ip.v4.dst_ip);
+		ice_pkt_insert_u16(loc, ICE_UDP4_NO_MAC_SRC_PORT_OFFSET,
+				   input->ip.v4.dst_port);
+		break;
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP:
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP:
+		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_DST_ADDR_OFFSET,
+				   input->ip.v4.src_ip);
+		ice_pkt_insert_u16(loc, ICE_TCP4_NO_MAC_DST_PORT_OFFSET,
+				   input->ip.v4.src_port);
+		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
+				   input->ip.v4.dst_ip);
+		ice_pkt_insert_u16(loc, ICE_TCP4_NO_MAC_SRC_PORT_OFFSET,
+				   input->ip.v4.dst_port);
+		break;
 	case ICE_FLTR_PTYPE_NONF_IPV6_GTPU:
 	case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER:
 		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index 37875cb94a..e8af2bb0e5 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -14,6 +14,9 @@
 #define ICE_IP_PROTO_IP			0
 #define ICE_IP_PROTO_ESP		50
 
+#define ICE_FDIR_GTPU_IP_INNER_PKT_OFF 50
+#define ICE_FDIR_GTPU_EH_INNER_PKT_OFF 58
+
 #define ICE_FDIR_TUN_PKT_OFF		50
 #define ICE_FDIR_MAX_RAW_PKT_SIZE	(512 + ICE_FDIR_TUN_PKT_OFF)
 #define ICE_FDIR_BUF_FULL_MARGIN	10
@@ -43,6 +46,13 @@
 #define ICE_IPV6_TC_OFFSET		14
 #define ICE_IPV6_HLIM_OFFSET		21
 #define ICE_IPV6_PROTO_OFFSET		20
+/* For TUN inner (without inner MAC) */
+#define ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET	12
+#define ICE_IPV4_NO_MAC_DST_ADDR_OFFSET	16
+#define ICE_TCP4_NO_MAC_SRC_PORT_OFFSET	20
+#define ICE_TCP4_NO_MAC_DST_PORT_OFFSET	22
+#define ICE_UDP4_NO_MAC_SRC_PORT_OFFSET	20
+#define ICE_UDP4_NO_MAC_DST_PORT_OFFSET	22
 #define ICE_IPV4_GTPU_TEID_OFFSET	46
 #define ICE_IPV4_GTPU_QFI_OFFSET	56
 #define ICE_IPV6_GTPU_TEID_OFFSET	66
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 05/14] net/ice/base: expose link configuration error
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (3 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 04/14] net/ice/base: enable GTPU inner L3/L4 for FDIR Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 06/14] net/ice/base: enable more GTPU inner L3 fields for FDIR Qi Zhang
                   ` (9 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Jeb Cramer

Store the link_cfg_err byte in order to determine whether an unsupported
power configuration is preventing link establishment.

Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_adminq_cmd.h | 1 +
 drivers/net/ice/base/ice_common.c     | 1 +
 drivers/net/ice/base/ice_type.h       | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index a31c27a633..4b78da92b5 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1513,6 +1513,7 @@ struct ice_aqc_get_link_status_data {
 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR	BIT(4)
 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED	BIT(5)
 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE	BIT(6)
+#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT	BIT(7)
 	u8 link_info;
 #define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
 #define ICE_AQ_LINK_FAULT		BIT(1)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index bef7c83512..1546309da1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -429,6 +429,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
 	li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
 	*hw_media_type = ice_get_media_type(pi);
 	li->link_info = link_data.link_info;
+	li->link_cfg_err = link_data.link_cfg_err;
 	li->an_info = link_data.an_info;
 	li->ext_info = link_data.ext_info;
 	li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 414424b66e..102c209286 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -248,6 +248,7 @@ struct ice_link_status {
 	u16 max_frame_size;
 	u16 link_speed;
 	u16 req_speeds;
+	u8 link_cfg_err;
 	u8 lse_ena;	/* Link Status Event notification */
 	u8 link_info;
 	u8 an_info;
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 06/14] net/ice/base: enable more GTPU inner L3 fields for FDIR
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (4 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 05/14] net/ice/base: expose link configuration error Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 07/14] net/ice/base: support for switch filter (GTP tunnel+IP flow) Qi Zhang
                   ` (8 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang

Add support for FDIR filter by GTPU inner L3 fields
(i.e., tos, ttl, proto).

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_fdir.c | 8 ++++++++
 drivers/net/ice/base/ice_fdir.h | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 2c479dfbd4..3df3de1bdb 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -1528,6 +1528,10 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 				   input->ip.v4.src_ip);
 		ice_pkt_insert_u32(loc, ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET,
 				   input->ip.v4.dst_ip);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET, input->ip.v4.tos);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_PROTO_OFFSET,
+				  input->ip.v4.proto);
 		break;
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH:
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW:
@@ -1553,6 +1557,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 				   input->ip.v4.dst_ip);
 		ice_pkt_insert_u16(loc, ICE_UDP4_NO_MAC_SRC_PORT_OFFSET,
 				   input->ip.v4.dst_port);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET, input->ip.v4.tos);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);
 		break;
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
 	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP:
@@ -1566,6 +1572,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 				   input->ip.v4.dst_ip);
 		ice_pkt_insert_u16(loc, ICE_TCP4_NO_MAC_SRC_PORT_OFFSET,
 				   input->ip.v4.dst_port);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET, input->ip.v4.tos);
+		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);
 		break;
 	case ICE_FLTR_PTYPE_NONF_IPV6_GTPU:
 	case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER:
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index e8af2bb0e5..e236f13f05 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -47,6 +47,9 @@
 #define ICE_IPV6_HLIM_OFFSET		21
 #define ICE_IPV6_PROTO_OFFSET		20
 /* For TUN inner (without inner MAC) */
+#define ICE_IPV4_NO_MAC_TOS_OFFSET	1
+#define ICE_IPV4_NO_MAC_TTL_OFFSET	8
+#define ICE_IPV4_NO_MAC_PROTO_OFFSET	9
 #define ICE_IPV4_NO_MAC_SRC_ADDR_OFFSET	12
 #define ICE_IPV4_NO_MAC_DST_ADDR_OFFSET	16
 #define ICE_TCP4_NO_MAC_SRC_PORT_OFFSET	20
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 07/14] net/ice/base: support for switch filter (GTP tunnel+IP flow)
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (5 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 06/14] net/ice/base: enable more GTPU inner L3 fields for FDIR Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR Qi Zhang
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Kiran Patil

Enabled support for advanced switch filter to satisfy match criteria
such as: GTP tunnel + Inner IPv4[6]

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_protocol_type.h |   8 +-
 drivers/net/ice/base/ice_switch.c        | 114 ++++++++++++-----------
 2 files changed, 63 insertions(+), 59 deletions(-)

diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index d769ad0580..ee1f29d41f 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -75,10 +75,6 @@ enum ice_sw_tunnel_type {
 	ICE_SW_TUN_GTP,
 	ICE_SW_TUN_IPV4_GTPU_NO_PAY,
 	ICE_SW_TUN_IPV6_GTPU_NO_PAY,
-	ICE_SW_TUN_IPV4_GTPU_IPV4,
-	ICE_SW_TUN_IPV4_GTPU_IPV6,
-	ICE_SW_TUN_IPV6_GTPU_IPV4,
-	ICE_SW_TUN_IPV6_GTPU_IPV6,
 	ICE_SW_TUN_PPPOE,
 	ICE_SW_TUN_PPPOE_PAY,
 	ICE_SW_TUN_PPPOE_IPV4,
@@ -109,6 +105,10 @@ enum ice_sw_tunnel_type {
 	ICE_SW_TUN_PPPOE_PAY_QINQ,
 	ICE_SW_TUN_PPPOE_IPV4_QINQ,
 	ICE_SW_TUN_PPPOE_IPV6_QINQ,
+	ICE_SW_TUN_IPV4_GTPU_IPV4,
+	ICE_SW_TUN_IPV4_GTPU_IPV6,
+	ICE_SW_TUN_IPV6_GTPU_IPV4,
+	ICE_SW_TUN_IPV6_GTPU_IPV6,
 	ICE_ALL_TUNNELS /* All tunnel types including NVGRE */
 };
 
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 4568242c10..2d0dd4b28c 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -912,39 +912,7 @@ static const u8 dummy_ipv6_gtpu_ipv6_udp_packet[] = {
 	0x00, 0x00, /* 2 bytes for 4 byte alignment */
 };
 
-static const struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = {
-	{ ICE_MAC_OFOS,		0 },
-	{ ICE_IPV4_OFOS,	14 },
-	{ ICE_UDP_OF,		34 },
-	{ ICE_GTP,		42 },
-	{ ICE_PROTOCOL_LAST,	0 },
-};
-
-static const u8 dummy_udp_gtp_packet[] = {
-	0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
-	0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00,
-	0x08, 0x00,
-
-	0x45, 0x00, 0x00, 0x30, /* ICE_IPV4_OFOS 14 */
-	0x00, 0x00, 0x00, 0x00,
-	0x00, 0x11, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00,
-
-	0x00, 0x00, 0x08, 0x68, /* ICE_UDP_OF 34 */
-	0x00, 0x1c, 0x00, 0x00,
-
-	0x34, 0xff, 0x00, 0x0c, /* ICE_GTP 42 */
-	0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x85,
-
-	0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
-	0x00, 0x00, 0x00, 0x00,
-};
-
-static const
-struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = {
+static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = {
 	{ ICE_MAC_OFOS,		0 },
 	{ ICE_IPV4_OFOS,	14 },
 	{ ICE_UDP_OF,		34 },
@@ -1126,8 +1094,38 @@ static const u8 dummy_ipv6_gtpu_ipv6_packet[] = {
 	0x00, 0x00,
 };
 
-static const
-struct ice_dummy_pkt_offsets dummy_ipv4_gtp_no_pay_packet_offsets[] = {
+static const struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = {
+	{ ICE_MAC_OFOS,		0 },
+	{ ICE_IPV4_OFOS,	14 },
+	{ ICE_UDP_OF,		34 },
+	{ ICE_GTP,		42 },
+	{ ICE_PROTOCOL_LAST,	0 },
+};
+
+static const u8 dummy_udp_gtp_packet[] = {
+	0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+	0x08, 0x00,
+
+	0x45, 0x00, 0x00, 0x30, /* ICE_IPV4_OFOS 14 */
+	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x11, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+
+	0x00, 0x00, 0x08, 0x68, /* ICE_UDP_OF 34 */
+	0x00, 0x1c, 0x00, 0x00,
+
+	0x34, 0xff, 0x00, 0x0c, /* ICE_GTP 42 */
+	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x85,
+
+	0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
+	0x00, 0x00, 0x00, 0x00,
+};
+
+static const struct ice_dummy_pkt_offsets dummy_ipv4_gtp_no_pay_packet_offsets[] = {
 	{ ICE_MAC_OFOS,		0 },
 	{ ICE_IPV4_OFOS,	14 },
 	{ ICE_UDP_OF,		34 },
@@ -7808,26 +7806,6 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
 		*pkt_len = sizeof(dummy_ipv6_gtpu_ipv6_packet);
 		*offsets = dummy_ipv6_gtp_no_pay_packet_offsets;
 		return;
-	} else if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV4) {
-		*pkt = dummy_ipv4_gtpu_ipv4_packet;
-		*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_packet);
-		*offsets = dummy_ipv4_gtpu_ipv4_packet_offsets;
-		return;
-	} else if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV6) {
-		*pkt = dummy_ipv4_gtpu_ipv6_packet;
-		*pkt_len = sizeof(dummy_ipv4_gtpu_ipv6_packet);
-		*offsets = dummy_ipv4_gtpu_ipv6_packet_offsets;
-		return;
-	} else if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV4) {
-		*pkt = dummy_ipv6_gtpu_ipv4_packet;
-		*pkt_len = sizeof(dummy_ipv6_gtpu_ipv4_packet);
-		*offsets = dummy_ipv6_gtpu_ipv4_packet_offsets;
-		return;
-	} else if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV6) {
-		*pkt = dummy_ipv6_gtpu_ipv6_packet;
-		*pkt_len = sizeof(dummy_ipv6_gtpu_ipv6_packet);
-		*offsets = dummy_ipv6_gtpu_ipv6_packet_offsets;
-		return;
 	}
 
 	if (tun_type == ICE_SW_TUN_IPV4_ESP) {
@@ -7976,6 +7954,32 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
 		return;
 	}
 
+	/* Support GTP tunnel + L3 */
+	if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV4) {
+		*pkt = dummy_ipv4_gtpu_ipv4_packet;
+		*pkt_len = sizeof(dummy_ipv4_gtpu_ipv4_packet);
+		*offsets = dummy_ipv4_gtpu_ipv4_packet_offsets;
+		return;
+	}
+	if (tun_type == ICE_SW_TUN_IPV4_GTPU_IPV6) {
+		*pkt = dummy_ipv4_gtpu_ipv6_packet;
+		*pkt_len = sizeof(dummy_ipv4_gtpu_ipv6_packet);
+		*offsets = dummy_ipv4_gtpu_ipv6_packet_offsets;
+		return;
+	}
+	if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV4) {
+		*pkt = dummy_ipv6_gtpu_ipv4_packet;
+		*pkt_len = sizeof(dummy_ipv6_gtpu_ipv4_packet);
+		*offsets = dummy_ipv6_gtpu_ipv4_packet_offsets;
+		return;
+	}
+	if (tun_type == ICE_SW_TUN_IPV6_GTPU_IPV6) {
+		*pkt = dummy_ipv6_gtpu_ipv6_packet;
+		*pkt_len = sizeof(dummy_ipv6_gtpu_ipv6_packet);
+		*offsets = dummy_ipv6_gtpu_ipv6_packet_offsets;
+		return;
+	}
+
 	if (tun_type == ICE_ALL_TUNNELS) {
 		*pkt = dummy_gre_udp_packet;
 		*pkt_len = sizeof(dummy_gre_udp_packet);
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (6 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 07/14] net/ice/base: support for switch filter (GTP tunnel+IP flow) Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 09/14] net/ice/base: fix incorrect payload indicator on PTYPE Qi Zhang
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang

Support IPV4_GTPU with inner IPV6/UDP/TCP for FDIR.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_fdir.c | 106 ++++++++++++++++++++++++++++++++
 drivers/net/ice/base/ice_fdir.h |   9 +++
 drivers/net/ice/base/ice_type.h |   3 +
 3 files changed, 118 insertions(+)

diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 3df3de1bdb..689e96da1e 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -249,6 +249,54 @@ static const u8 ice_fdir_icmp4_gtpu4_pkt[] = {
 	0x00, 0x00,
 };
 
+static const u8 ice_fdir_ipv6_gtpu4_pkt[] = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+	0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
+	0x24, 0x42, 0x30, 0xff, 0x00, 0x28, 0x00, 0x00,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_udp6_gtpu4_pkt[] = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+	0x00, 0x54, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x40,
+	0x4e, 0x3d, 0x30, 0xff, 0x00, 0x30, 0x00, 0x00,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,
+	0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+	0xff, 0xdc, 0x00, 0x00,
+};
+
+static const u8 ice_fdir_tcp6_gtpu4_pkt[] = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+	0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4e,
+	0x59, 0x08, 0x30, 0xff, 0x00, 0x3e, 0x00, 0x00,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,
+	0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
+	0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,
+};
+
 static const u8 ice_fdir_ipv6_gtpu6_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,
@@ -802,6 +850,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
 		sizeof(ice_fdir_ipv4_gtpu4_pkt),
 		ice_fdir_ipv4_gtpu4_pkt,
 	},
+	{
+		ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
+		sizeof(ice_fdir_ipv6_gtpu4_pkt),
+		ice_fdir_ipv6_gtpu4_pkt,
+		sizeof(ice_fdir_ipv6_gtpu4_pkt),
+		ice_fdir_ipv6_gtpu4_pkt,
+	},
+	{
+		ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
+		sizeof(ice_fdir_udp6_gtpu4_pkt),
+		ice_fdir_udp6_gtpu4_pkt,
+		sizeof(ice_fdir_udp6_gtpu4_pkt),
+		ice_fdir_udp6_gtpu4_pkt,
+	},
+	{
+		ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
+		sizeof(ice_fdir_tcp6_gtpu4_pkt),
+		ice_fdir_tcp6_gtpu4_pkt,
+		sizeof(ice_fdir_tcp6_gtpu4_pkt),
+		ice_fdir_tcp6_gtpu4_pkt,
+	},
 	{
 		ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
 		sizeof(ice_fdir_ipv6_gtpu6_pkt),
@@ -1391,6 +1460,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4:
 		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:
 		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:
+		case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:
 			ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,
 				   ice_fdir_pkt[idx].tun_pkt_len,
 				   ICE_NONDMA_TO_NONDMA);
@@ -1575,6 +1647,40 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,
 		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET, input->ip.v4.tos);
 		ice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);
 		break;
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:
+		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+					 input->ip.v6.src_ip);
+		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+					 input->ip.v6.dst_ip);
+		ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);
+		ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
+		ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_PROTO_OFFSET,
+				  input->ip.v6.proto);
+		break;
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:
+		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+					 input->ip.v6.src_ip);
+		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+					 input->ip.v6.dst_ip);
+		ice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_DST_PORT_OFFSET,
+				   input->ip.v6.src_port);
+		ice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_SRC_PORT_OFFSET,
+				   input->ip.v6.dst_port);
+		ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);
+		ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
+		break;
+	case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:
+		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,
+					 input->ip.v6.src_ip);
+		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,
+					 input->ip.v6.dst_ip);
+		ice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_DST_PORT_OFFSET,
+				   input->ip.v6.src_port);
+		ice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_SRC_PORT_OFFSET,
+				   input->ip.v6.dst_port);
+		ice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);
+		ice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);
+		break;
 	case ICE_FLTR_PTYPE_NONF_IPV6_GTPU:
 	case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER:
 		ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index e236f13f05..6573f96bc1 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -56,6 +56,15 @@
 #define ICE_TCP4_NO_MAC_DST_PORT_OFFSET	22
 #define ICE_UDP4_NO_MAC_SRC_PORT_OFFSET	20
 #define ICE_UDP4_NO_MAC_DST_PORT_OFFSET	22
+#define ICE_IPV6_NO_MAC_TC_OFFSET	0
+#define ICE_IPV6_NO_MAC_HLIM_OFFSET	7
+#define ICE_IPV6_NO_MAC_PROTO_OFFSET	6
+#define ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET	8
+#define ICE_IPV6_NO_MAC_DST_ADDR_OFFSET	24
+#define ICE_TCP6_NO_MAC_SRC_PORT_OFFSET	40
+#define ICE_TCP6_NO_MAC_DST_PORT_OFFSET	42
+#define ICE_UDP6_NO_MAC_SRC_PORT_OFFSET	40
+#define ICE_UDP6_NO_MAC_DST_PORT_OFFSET	42
 #define ICE_IPV4_GTPU_TEID_OFFSET	46
 #define ICE_IPV4_GTPU_QFI_OFFSET	56
 #define ICE_IPV6_GTPU_TEID_OFFSET	66
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 102c209286..2550e0e19f 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -316,6 +316,9 @@ enum ice_fltr_ptype {
 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
+	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
+	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
+	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 09/14] net/ice/base: fix incorrect payload indicator on PTYPE
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (7 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 10/14] net/ice/base: mark PTYPE 2 as reserved Qi Zhang
                   ` (5 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, stable, Jacob Keller

The entry for PTYPE 90 indicates that the payload is layer 3. This does
not match the specification in the datasheet which indicates the packet
is a MAC, IPv6, UDP packet, with a payload in layer 4.

Fix the lookup table to match the data sheet.

Fixes: 64e9587d5629 ("net/ice/base: add structures for Rx/Tx queues")
Cc: stable@dpdk.org

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 107826acd0..e0e79cad95 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1353,7 +1353,7 @@ static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {
 	/* Non Tunneled IPv6 */
 	ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 	ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
-	ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
+	ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 	ICE_PTT_UNUSED_ENTRY(91),
 	ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 	ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 10/14] net/ice/base: mark PTYPE 2 as reserved
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (8 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 09/14] net/ice/base: fix incorrect payload indicator on PTYPE Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 11/14] net/ice/base: add code to update boost TCAM for DVM Qi Zhang
                   ` (4 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Jacob Keller

The entry for PTYPE 2 in the ice_ptype_lkup table incorrectly states
that this is an L2 packet with no payload. According to the datasheet,
this PTYPE is actually unused and reserved.

Modify the lookup entry to indicate this is an unused entry that is
reserved.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index e0e79cad95..e24a1bb767 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1239,7 +1239,7 @@ static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {
 	/* L2 Packet types */
 	ICE_PTT_UNUSED_ENTRY(0),
 	ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
-	ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
+	ICE_PTT_UNUSED_ENTRY(2),
 	ICE_PTT_UNUSED_ENTRY(3),
 	ICE_PTT_UNUSED_ENTRY(4),
 	ICE_PTT_UNUSED_ENTRY(5),
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 11/14] net/ice/base: add code to update boost TCAM for DVM
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (9 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 10/14] net/ice/base: mark PTYPE 2 as reserved Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 12/14] net/ice/base: update GTPU EH dummy pkts for FDIR Qi Zhang
                   ` (3 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, Dan Nowlin

Add code to update boost TCAM entries to enable DVM. This requires
enabled DVM entries, and disabling SVM entries.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_flex_pipe.c | 223 +++++++++++++++++++++++----
 drivers/net/ice/base/ice_flex_pipe.h |   1 +
 drivers/net/ice/base/ice_flex_type.h |  13 ++
 drivers/net/ice/base/ice_type.h      |   2 +
 drivers/net/ice/base/ice_vlan_mode.c |   7 +
 5 files changed, 213 insertions(+), 33 deletions(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index cf470bc4f0..f429bfb0d1 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -7,9 +7,17 @@
 #include "ice_protocol_type.h"
 #include "ice_flow.h"
 
+/* For supporting double VLAN mode, it is necessary to enable or disable certain
+ * boost tcam entries. The metadata labels names that match the following
+ * prefixes will be saved to allow enabling double VLAN mode.
+ */
+#define ICE_DVM_PRE	"BOOST_MAC_VLAN_DVM"	/* enable these entries */
+#define ICE_SVM_PRE	"BOOST_MAC_VLAN_SVM"	/* disable these entries */
+
 /* To support tunneling entries by PF, the package will append the PF number to
  * the label; for example TNL_VXLAN_PF0, TNL_VXLAN_PF1, TNL_VXLAN_PF2, etc.
  */
+#define ICE_TNL_PRE	"TNL_"
 static const struct ice_tunnel_type_scan tnls[] = {
 	{ TNL_VXLAN,		"TNL_VXLAN_PF" },
 	{ TNL_GENEVE,		"TNL_GENEVE_PF" },
@@ -531,6 +539,57 @@ ice_enum_labels(struct ice_seg *ice_seg, u32 type, struct ice_pkg_enum *state,
 	return label->name;
 }
 
+/**
+ * ice_add_tunnel_hint
+ * @hw: pointer to the HW structure
+ * @label_name: label text
+ * @val: value of the tunnel port boost entry
+ */
+static void ice_add_tunnel_hint(struct ice_hw *hw, char *label_name, u16 val)
+{
+	if (hw->tnl.count < ICE_TUNNEL_MAX_ENTRIES) {
+		u16 i;
+
+		for (i = 0; tnls[i].type != TNL_LAST; i++) {
+			size_t len = strlen(tnls[i].label_prefix);
+
+			/* Look for matching label start, before continuing */
+			if (strncmp(label_name, tnls[i].label_prefix, len))
+				continue;
+
+			/* Make sure this label matches our PF. Note that the PF
+			 * character ('0' - '7') will be located where our
+			 * prefix string's null terminator is located.
+			 */
+			if ((label_name[len] - '0') == hw->pf_id) {
+				hw->tnl.tbl[hw->tnl.count].type = tnls[i].type;
+				hw->tnl.tbl[hw->tnl.count].valid = false;
+				hw->tnl.tbl[hw->tnl.count].in_use = false;
+				hw->tnl.tbl[hw->tnl.count].marked = false;
+				hw->tnl.tbl[hw->tnl.count].boost_addr = val;
+				hw->tnl.tbl[hw->tnl.count].port = 0;
+				hw->tnl.count++;
+				break;
+			}
+		}
+	}
+}
+
+/**
+ * ice_add_dvm_hint
+ * @hw: pointer to the HW structure
+ * @val: value of the boost entry
+ * @enable: true if entry needs to be enabled, or false if needs to be disabled
+ */
+static void ice_add_dvm_hint(struct ice_hw *hw, u16 val, bool enable)
+{
+	if (hw->dvm_upd.count < ICE_DVM_MAX_ENTRIES) {
+		hw->dvm_upd.tbl[hw->dvm_upd.count].boost_addr = val;
+		hw->dvm_upd.tbl[hw->dvm_upd.count].enable = enable;
+		hw->dvm_upd.count++;
+	}
+}
+
 /**
  * ice_init_pkg_hints
  * @hw: pointer to the HW structure
@@ -557,40 +616,34 @@ static void ice_init_pkg_hints(struct ice_hw *hw, struct ice_seg *ice_seg)
 	label_name = ice_enum_labels(ice_seg, ICE_SID_LBL_RXPARSER_TMEM, &state,
 				     &val);
 
-	while (label_name && hw->tnl.count < ICE_TUNNEL_MAX_ENTRIES) {
-		for (i = 0; tnls[i].type != TNL_LAST; i++) {
-			size_t len = strlen(tnls[i].label_prefix);
+	while (label_name) {
+		if (!strncmp(label_name, ICE_TNL_PRE, strlen(ICE_TNL_PRE)))
+			/* check for a tunnel entry */
+			ice_add_tunnel_hint(hw, label_name, val);
 
-			/* Look for matching label start, before continuing */
-			if (strncmp(label_name, tnls[i].label_prefix, len))
-				continue;
+		/* check for a dvm mode entry */
+		else if (!strncmp(label_name, ICE_DVM_PRE, strlen(ICE_DVM_PRE)))
+			ice_add_dvm_hint(hw, val, true);
 
-			/* Make sure this label matches our PF. Note that the PF
-			 * character ('0' - '7') will be located where our
-			 * prefix string's null terminator is located.
-			 */
-			if ((label_name[len] - '0') == hw->pf_id) {
-				hw->tnl.tbl[hw->tnl.count].type = tnls[i].type;
-				hw->tnl.tbl[hw->tnl.count].valid = false;
-				hw->tnl.tbl[hw->tnl.count].in_use = false;
-				hw->tnl.tbl[hw->tnl.count].marked = false;
-				hw->tnl.tbl[hw->tnl.count].boost_addr = val;
-				hw->tnl.tbl[hw->tnl.count].port = 0;
-				hw->tnl.count++;
-				break;
-			}
-		}
+		/* check for a svm mode entry */
+		else if (!strncmp(label_name, ICE_SVM_PRE, strlen(ICE_SVM_PRE)))
+			ice_add_dvm_hint(hw, val, false);
 
 		label_name = ice_enum_labels(NULL, 0, &state, &val);
 	}
 
-	/* Cache the appropriate boost TCAM entry pointers */
+	/* Cache the appropriate boost TCAM entry pointers for tunnels */
 	for (i = 0; i < hw->tnl.count; i++) {
 		ice_find_boost_entry(ice_seg, hw->tnl.tbl[i].boost_addr,
 				     &hw->tnl.tbl[i].boost_entry);
 		if (hw->tnl.tbl[i].boost_entry)
 			hw->tnl.tbl[i].valid = true;
 	}
+
+	/* Cache the appropriate boost TCAM entry pointers for DVM and SVM */
+	for (i = 0; i < hw->dvm_upd.count; i++)
+		ice_find_boost_entry(ice_seg, hw->dvm_upd.tbl[i].boost_addr,
+				     &hw->dvm_upd.tbl[i].boost_entry);
 }
 
 /* Key creation */
@@ -995,26 +1048,21 @@ ice_find_seg_in_pkg(struct ice_hw *hw, u32 seg_type,
 }
 
 /**
- * ice_update_pkg
+ * ice_update_pkg_no_lock
  * @hw: pointer to the hardware structure
  * @bufs: pointer to an array of buffers
  * @count: the number of buffers in the array
- *
- * Obtains change lock and updates package.
  */
-enum ice_status
-ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
+static enum ice_status
+ice_update_pkg_no_lock(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
 {
-	enum ice_status status;
-	u32 offset, info, i;
-
-	status = ice_acquire_change_lock(hw, ICE_RES_WRITE);
-	if (status)
-		return status;
+	enum ice_status status = ICE_SUCCESS;
+	u32 i;
 
 	for (i = 0; i < count; i++) {
 		struct ice_buf_hdr *bh = (struct ice_buf_hdr *)(bufs + i);
 		bool last = ((i + 1) == count);
+		u32 offset, info;
 
 		status = ice_aq_update_pkg(hw, bh, LE16_TO_CPU(bh->data_end),
 					   last, &offset, &info, NULL);
@@ -1026,6 +1074,28 @@ ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
 		}
 	}
 
+	return status;
+}
+
+/**
+ * ice_update_pkg
+ * @hw: pointer to the hardware structure
+ * @bufs: pointer to an array of buffers
+ * @count: the number of buffers in the array
+ *
+ * Obtains change lock and updates package.
+ */
+enum ice_status
+ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
+{
+	enum ice_status status;
+
+	status = ice_acquire_change_lock(hw, ICE_RES_WRITE);
+	if (status)
+		return status;
+
+	status = ice_update_pkg_no_lock(hw, bufs, count);
+
 	ice_release_change_lock(hw);
 
 	return status;
@@ -2202,6 +2272,93 @@ ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
 	return res;
 }
 
+/**
+ * ice_upd_dvm_boost_entry
+ * @hw: pointer to the HW structure
+ * @entry: pointer to double vlan boost entry info
+ */
+static enum ice_status
+ice_upd_dvm_boost_entry(struct ice_hw *hw, struct ice_dvm_entry *entry)
+{
+	struct ice_boost_tcam_section *sect_rx, *sect_tx;
+	enum ice_status status = ICE_ERR_MAX_LIMIT;
+	struct ice_buf_build *bld;
+	u8 val, dc, nm;
+
+	bld = ice_pkg_buf_alloc(hw);
+	if (!bld)
+		return ICE_ERR_NO_MEMORY;
+
+	/* allocate 2 sections, one for Rx parser, one for Tx parser */
+	if (ice_pkg_buf_reserve_section(bld, 2))
+		goto ice_upd_dvm_boost_entry_err;
+
+	sect_rx = (struct ice_boost_tcam_section *)
+		ice_pkg_buf_alloc_section(bld, ICE_SID_RXPARSER_BOOST_TCAM,
+					  ice_struct_size(sect_rx, tcam, 1));
+	if (!sect_rx)
+		goto ice_upd_dvm_boost_entry_err;
+	sect_rx->count = CPU_TO_LE16(1);
+
+	sect_tx = (struct ice_boost_tcam_section *)
+		ice_pkg_buf_alloc_section(bld, ICE_SID_TXPARSER_BOOST_TCAM,
+					  ice_struct_size(sect_tx, tcam, 1));
+	if (!sect_tx)
+		goto ice_upd_dvm_boost_entry_err;
+	sect_tx->count = CPU_TO_LE16(1);
+
+	/* copy original boost entry to update package buffer */
+	ice_memcpy(sect_rx->tcam, entry->boost_entry, sizeof(*sect_rx->tcam),
+		   ICE_NONDMA_TO_NONDMA);
+
+	/* re-write the don't care and never match bits accordingly */
+	if (entry->enable) {
+		/* all bits are don't care */
+		val = 0x00;
+		dc = 0xFF;
+		nm = 0x00;
+	} else {
+		/* disable, one never match bit, the rest are don't care */
+		val = 0x00;
+		dc = 0xF7;
+		nm = 0x08;
+	}
+
+	ice_set_key((u8 *)&sect_rx->tcam[0].key, sizeof(sect_rx->tcam[0].key),
+		    &val, NULL, &dc, &nm, 0, sizeof(u8));
+
+	/* exact copy of entry to Tx section entry */
+	ice_memcpy(sect_tx->tcam, sect_rx->tcam, sizeof(*sect_tx->tcam),
+		   ICE_NONDMA_TO_NONDMA);
+
+	status = ice_update_pkg_no_lock(hw, ice_pkg_buf(bld), 1);
+
+ice_upd_dvm_boost_entry_err:
+	ice_pkg_buf_free(hw, bld);
+
+	return status;
+}
+
+/**
+ * ice_set_dvm_boost_entries
+ * @hw: pointer to the HW structure
+ *
+ * Enable double vlan by updating the appropriate boost tcam entries.
+ */
+enum ice_status ice_set_dvm_boost_entries(struct ice_hw *hw)
+{
+	enum ice_status status;
+	u16 i;
+
+	for (i = 0; i < hw->dvm_upd.count; i++) {
+		status = ice_upd_dvm_boost_entry(hw, &hw->dvm_upd.tbl[i]);
+		if (status)
+			return status;
+	}
+
+	return ICE_SUCCESS;
+}
+
 /**
  * ice_create_tunnel
  * @hw: pointer to the HW structure
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 58e3c1d1ec..b690be75fc 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -49,6 +49,7 @@ ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
 			 u16 *port);
 enum ice_status
 ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
+enum ice_status ice_set_dvm_boost_entries(struct ice_hw *hw);
 enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);
 bool ice_tunnel_port_in_use(struct ice_hw *hw, u16 port, u16 *index);
 bool
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index c7f92b9150..63a2cb8bc4 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -675,6 +675,19 @@ struct ice_tunnel_table {
 	u16 count;
 };
 
+struct ice_dvm_entry {
+	u16 boost_addr;
+	u16 enable;
+	struct ice_boost_tcam_entry *boost_entry;
+};
+
+#define ICE_DVM_MAX_ENTRIES	48
+
+struct ice_dvm_table {
+	struct ice_dvm_entry tbl[ICE_DVM_MAX_ENTRIES];
+	u16 count;
+};
+
 struct ice_pkg_es {
 	__le16 count;
 	__le16 offset;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2550e0e19f..a6599363f9 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -992,6 +992,8 @@ struct ice_hw {
 	/* tunneling info */
 	struct ice_lock tnl_lock;
 	struct ice_tunnel_table tnl;
+	/* dvm boost update information */
+	struct ice_dvm_table dvm_upd;
 
 	struct ice_acl_tbl *acl_tbl;
 	struct ice_fd_hw_prof **acl_prof;
diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c
index 460c4f902b..4ba78ed4cd 100644
--- a/drivers/net/ice/base/ice_vlan_mode.c
+++ b/drivers/net/ice/base/ice_vlan_mode.c
@@ -312,6 +312,13 @@ static enum ice_status ice_set_dvm(struct ice_hw *hw)
 		return status;
 	}
 
+	status = ice_set_dvm_boost_entries(hw);
+	if (status) {
+		ice_debug(hw, ICE_DBG_INIT, "Failed to set boost TCAM entries for double VLAN mode, status %d\n",
+			  status);
+		return status;
+	}
+
 	return ICE_SUCCESS;
 }
 
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 12/14] net/ice/base: update GTPU EH dummy pkts for FDIR
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (10 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 11/14] net/ice/base: add code to update boost TCAM for DVM Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 13/14] net/ice/base: fix uninitialized struct Qi Zhang
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang

Update GTPU EH dummy pkts for FDIR, including EH/DL/UL.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_fdir.c | 176 +++++++++++++++-----------------
 1 file changed, 84 insertions(+), 92 deletions(-)

diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 689e96da1e..2b39c13127 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -100,138 +100,130 @@ static const u8 ice_fdir_tcp4_gtpu4_pkt[] = {
 static const u8 ice_fdir_ipv4_gtpu4_eh_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x44, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x30,
-	0x76, 0x6c, 0x34, 0xff, 0x00, 0x20, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x14, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
-	0x3a, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+	0xba, 0x1d, 0x34, 0xff, 0x00, 0x1e, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_udp4_gtpu4_eh_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
-	0xb7, 0x1a, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x1c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x3a, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
-	0xbe, 0xc7, 0x00, 0x00,
+	0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xa0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x36,
+	0xb8, 0x23, 0x34, 0xff, 0x00, 0x26, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x0a, 0x01, 0xd8, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_tcp4_gtpu4_eh_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44,
-	0xb6, 0xf7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
-	0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
-	0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+	0xb8, 0x00, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0xde,
+	0x00, 0x00, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_ipv4_gtpu4_eh_dw_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44,
-	0xb6, 0xf7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
-	0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
-	0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+	0xba, 0x1d, 0x34, 0xff, 0x00, 0x1e, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_udp4_gtpu4_eh_dw_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
-	0xb7, 0x1a, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x1c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x3a, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
-	0xbe, 0xc7, 0x00, 0x00,
+	0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xa0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x36,
+	0xb8, 0x23, 0x34, 0xff, 0x00, 0x26, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x0a, 0x01, 0xd8, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_tcp4_gtpu4_eh_dw_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44,
-	0xb6, 0xf7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
-	0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
-	0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+	0xb8, 0x00, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x00,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0xde,
+	0x00, 0x00, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_ipv4_gtpu4_eh_up_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x44, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x30,
-	0x76, 0x5c, 0x34, 0xff, 0x00, 0x20, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x10,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x14, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00,
-	0x3a, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x2e,
+	0xba, 0x0d, 0x34, 0xff, 0x00, 0x1e, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x16, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x00, 0x7c, 0xe5, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_udp4_gtpu4_eh_up_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,
-	0xb7, 0x0a, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x10,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x1c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x3a, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
-	0xbe, 0xc7, 0x00, 0x00,
+	0x00, 0x4a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0xa0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x36,
+	0xb8, 0x13, 0x34, 0xff, 0x00, 0x26, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x1e, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x11, 0x7c, 0xcc, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x0a, 0x01, 0xd8, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_tcp4_gtpu4_eh_up_pkt[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
-	0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
-	0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44,
-	0xb6, 0xe7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x10,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00,
-	0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
-	0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,
-	0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x56, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+	0x7c, 0x94, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+	0x00, 0x01, 0x08, 0x68, 0x08, 0x68, 0x00, 0x42,
+	0xb7, 0xf0, 0x34, 0xff, 0x00, 0x32, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x01, 0x10,
+	0x00, 0x00, 0x45, 0x00, 0x00, 0x2a, 0x00, 0x01,
+	0x00, 0x00, 0x40, 0x06, 0x7c, 0xcb, 0x7f, 0x00,
+	0x00, 0x01, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x50, 0x02, 0x20, 0x00, 0x91, 0xde,
+	0x00, 0x00, 0x00, 0x00,
 };
 
 static const u8 ice_fdir_icmp4_gtpu4_pkt[] = {
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 13/14] net/ice/base: fix uninitialized struct
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (11 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 12/14] net/ice/base: update GTPU EH dummy pkts for FDIR Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 14/14] net/ice/base: cleanup fltr list in case of allocation issues Qi Zhang
  2021-03-04  5:31 ` [dpdk-dev] [PATCH 00/14] ice: base code update Yang, Qiming
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang
  Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, stable, Jesse Brandeburg

One of the structs being used for ACL counter rules was allocated on
the stack and left uninitialized.  Rather than depending on
undefined behavior around the .amount member during rule removal,
just leave a comment and initialize the struct to zero, as this is a
slow path call anyway. This bug could have caused silent failures
during counter removal.

Fixes: f3202a097f12 ("net/ice/base: add ACL module")
Cc: stable@dpdk.org

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_flow.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index a081fbe5a4..d123206fc6 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -1795,9 +1795,14 @@ ice_flow_acl_free_act_cntr(struct ice_hw *hw, struct ice_flow_action *acts,
 		if (acts[i].type == ICE_FLOW_ACT_CNTR_PKT ||
 		    acts[i].type == ICE_FLOW_ACT_CNTR_BYTES ||
 		    acts[i].type == ICE_FLOW_ACT_CNTR_PKT_BYTES) {
-			struct ice_acl_cntrs cntrs;
+			struct ice_acl_cntrs cntrs = { 0 };
 			enum ice_status status;
 
+			/* amount is unused in the dealloc path but the common
+			 * parameter check routine wants a value set, as zero
+			 * is invalid for the check. Just set it.
+			 */
+			cntrs.amount = 1;
 			cntrs.bank = 0; /* Only bank0 for the moment */
 			cntrs.first_cntr =
 					LE16_TO_CPU(acts[i].data.acl_act.value);
@@ -2396,7 +2401,7 @@ ice_flow_acl_check_actions(struct ice_hw *hw, struct ice_flow_action *acts,
 		if (acts[i].type == ICE_FLOW_ACT_CNTR_PKT ||
 		    acts[i].type == ICE_FLOW_ACT_CNTR_BYTES ||
 		    acts[i].type == ICE_FLOW_ACT_CNTR_PKT_BYTES) {
-			struct ice_acl_cntrs cntrs;
+			struct ice_acl_cntrs cntrs = { 0 };
 			enum ice_status status;
 
 			cntrs.amount = 1;
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 14/14] net/ice/base: cleanup fltr list in case of allocation issues
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (12 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 13/14] net/ice/base: fix uninitialized struct Qi Zhang
@ 2021-03-02  7:23 ` Qi Zhang
  2021-03-04  5:31 ` [dpdk-dev] [PATCH 00/14] ice: base code update Yang, Qiming
  14 siblings, 0 replies; 17+ messages in thread
From: Qi Zhang @ 2021-03-02  7:23 UTC (permalink / raw)
  To: qiming.yang; +Cc: dev, haiyue.wang, junfeng.guo, Qi Zhang, stable, Robert Malz

When ice_remove_vsi_lkup_fltr is called, by calling
ice_add_to_vsi_fltr_list local copy of vsi filter list
is created. If any issues during creation of vsi filter
list occurs it up for the caller to free already
allocated memory. This patch ensures proper memory
deallocation in these cases.

Fixes: c7dd15931183 ("net/ice/base: add virtual switch code")
Cc: stable@dpdk.org

Signed-off-by: Robert Malz <robertx.malz@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_switch.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 2d0dd4b28c..3dc764266b 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6078,7 +6078,7 @@ ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,
 					  &remove_list_head);
 	ice_release_lock(rule_lock);
 	if (status)
-		return;
+		goto free_fltr_list;
 
 	switch (lkup) {
 	case ICE_SW_LKUP_MAC:
@@ -6106,6 +6106,7 @@ ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,
 		break;
 	}
 
+free_fltr_list:
 	LIST_FOR_EACH_ENTRY_SAFE(fm_entry, tmp, &remove_list_head,
 				 ice_fltr_list_entry, list_entry) {
 		LIST_DEL(&fm_entry->list_entry);
-- 
2.26.2


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 00/14] ice: base code update
  2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
                   ` (13 preceding siblings ...)
  2021-03-02  7:23 ` [dpdk-dev] [PATCH 14/14] net/ice/base: cleanup fltr list in case of allocation issues Qi Zhang
@ 2021-03-04  5:31 ` Yang, Qiming
  2021-03-05  8:39   ` Zhang, Qi Z
  14 siblings, 1 reply; 17+ messages in thread
From: Yang, Qiming @ 2021-03-04  5:31 UTC (permalink / raw)
  To: Zhang, Qi Z; +Cc: dev, Wang, Haiyue, Guo, Junfeng

Hi,

> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: 2021年3月2日 15:24
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: dev@dpdk.org; Wang, Haiyue <haiyue.wang@intel.com>; Guo, Junfeng
> <junfeng.guo@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> Subject: [PATCH 00/14] ice: base code update
> 
> Main change:
> 1. Support GTPU inner l3/l4 for FDIR
> 2. Support GTPU extention header for FDIR 3. Support switch filter (GTPU
> tunnel + IP flow) 4. couple bug fixes.
> 
> Qi Zhang (14):
>   net/ice/base: add firmware log support
>   net/ice/base: signed external device package programming
>   net/ice/base: post update double reset solution restriction
>   net/ice/base: enable GTPU inner L3/L4 for FDIR
>   net/ice/base: expose link configuration error
>   net/ice/base: enable more GTPU inner L3 fields for FDIR
>   net/ice/base: support for switch filter (GTP tunnel+IP flow)
>   net/ice/base: support GTPU IP inner IPv6 for FDIR
>   net/ice/base: fix incorrect payload indicator on PTYPE
>   net/ice/base: mark PTYPE 2 as reserved
>   net/ice/base: add code to update boost TCAM for DVM
>   net/ice/base: update GTPU EH dummy pkts for FDIR
>   net/ice/base: fix uninitialized struct
>   net/ice/base: cleanup fltr list in case of allocation issues
> 
>  drivers/net/ice/base/ice_adminq_cmd.h    |  83 ++++-
>  drivers/net/ice/base/ice_common.c        |   1 +
>  drivers/net/ice/base/ice_fdir.c          | 412 ++++++++++++++++-------
>  drivers/net/ice/base/ice_fdir.h          |  22 ++
>  drivers/net/ice/base/ice_flex_pipe.c     | 223 ++++++++++--
>  drivers/net/ice/base/ice_flex_pipe.h     |   1 +
>  drivers/net/ice/base/ice_flex_type.h     |  13 +
>  drivers/net/ice/base/ice_flow.c          |   9 +-
>  drivers/net/ice/base/ice_lan_tx_rx.h     |   4 +-
>  drivers/net/ice/base/ice_protocol_type.h |   8 +-
>  drivers/net/ice/base/ice_switch.c        | 117 ++++---
>  drivers/net/ice/base/ice_type.h          |   6 +
>  drivers/net/ice/base/ice_vlan_mode.c     |   7 +
>  13 files changed, 679 insertions(+), 227 deletions(-)
> 
> --
> 2.26.2

Acked-by: Qiming Yang <qiming.yang@intel.com>

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 00/14] ice: base code update
  2021-03-04  5:31 ` [dpdk-dev] [PATCH 00/14] ice: base code update Yang, Qiming
@ 2021-03-05  8:39   ` Zhang, Qi Z
  0 siblings, 0 replies; 17+ messages in thread
From: Zhang, Qi Z @ 2021-03-05  8:39 UTC (permalink / raw)
  To: Yang, Qiming; +Cc: dev, Wang, Haiyue, Guo, Junfeng



> -----Original Message-----
> From: Yang, Qiming <qiming.yang@intel.com>
> Sent: Thursday, March 4, 2021 1:32 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Wang, Haiyue <haiyue.wang@intel.com>; Guo, Junfeng
> <junfeng.guo@intel.com>
> Subject: RE: [PATCH 00/14] ice: base code update
> 
> Hi,
> 
> > -----Original Message-----
> > From: Zhang, Qi Z <qi.z.zhang@intel.com>
> > Sent: 2021年3月2日 15:24
> > To: Yang, Qiming <qiming.yang@intel.com>
> > Cc: dev@dpdk.org; Wang, Haiyue <haiyue.wang@intel.com>; Guo, Junfeng
> > <junfeng.guo@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> > Subject: [PATCH 00/14] ice: base code update
> >
> > Main change:
> > 1. Support GTPU inner l3/l4 for FDIR
> > 2. Support GTPU extention header for FDIR 3. Support switch filter
> > (GTPU tunnel + IP flow) 4. couple bug fixes.
> >
> > Qi Zhang (14):
> >   net/ice/base: add firmware log support
> >   net/ice/base: signed external device package programming
> >   net/ice/base: post update double reset solution restriction
> >   net/ice/base: enable GTPU inner L3/L4 for FDIR
> >   net/ice/base: expose link configuration error
> >   net/ice/base: enable more GTPU inner L3 fields for FDIR
> >   net/ice/base: support for switch filter (GTP tunnel+IP flow)
> >   net/ice/base: support GTPU IP inner IPv6 for FDIR
> >   net/ice/base: fix incorrect payload indicator on PTYPE
> >   net/ice/base: mark PTYPE 2 as reserved
> >   net/ice/base: add code to update boost TCAM for DVM
> >   net/ice/base: update GTPU EH dummy pkts for FDIR
> >   net/ice/base: fix uninitialized struct
> >   net/ice/base: cleanup fltr list in case of allocation issues
> >
> >  drivers/net/ice/base/ice_adminq_cmd.h    |  83 ++++-
> >  drivers/net/ice/base/ice_common.c        |   1 +
> >  drivers/net/ice/base/ice_fdir.c          | 412 ++++++++++++++++-------
> >  drivers/net/ice/base/ice_fdir.h          |  22 ++
> >  drivers/net/ice/base/ice_flex_pipe.c     | 223 ++++++++++--
> >  drivers/net/ice/base/ice_flex_pipe.h     |   1 +
> >  drivers/net/ice/base/ice_flex_type.h     |  13 +
> >  drivers/net/ice/base/ice_flow.c          |   9 +-
> >  drivers/net/ice/base/ice_lan_tx_rx.h     |   4 +-
> >  drivers/net/ice/base/ice_protocol_type.h |   8 +-
> >  drivers/net/ice/base/ice_switch.c        | 117 ++++---
> >  drivers/net/ice/base/ice_type.h          |   6 +
> >  drivers/net/ice/base/ice_vlan_mode.c     |   7 +
> >  13 files changed, 679 insertions(+), 227 deletions(-)
> >
> > --
> > 2.26.2
> 
> Acked-by: Qiming Yang <qiming.yang@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi


^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2021-03-05  8:39 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-02  7:23 [dpdk-dev] [PATCH 00/14] ice: base code update Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 01/14] net/ice/base: add firmware log support Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 02/14] net/ice/base: signed external device package programming Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 03/14] net/ice/base: post update double reset solution restriction Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 04/14] net/ice/base: enable GTPU inner L3/L4 for FDIR Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 05/14] net/ice/base: expose link configuration error Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 06/14] net/ice/base: enable more GTPU inner L3 fields for FDIR Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 07/14] net/ice/base: support for switch filter (GTP tunnel+IP flow) Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 09/14] net/ice/base: fix incorrect payload indicator on PTYPE Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 10/14] net/ice/base: mark PTYPE 2 as reserved Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 11/14] net/ice/base: add code to update boost TCAM for DVM Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 12/14] net/ice/base: update GTPU EH dummy pkts for FDIR Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 13/14] net/ice/base: fix uninitialized struct Qi Zhang
2021-03-02  7:23 ` [dpdk-dev] [PATCH 14/14] net/ice/base: cleanup fltr list in case of allocation issues Qi Zhang
2021-03-04  5:31 ` [dpdk-dev] [PATCH 00/14] ice: base code update Yang, Qiming
2021-03-05  8:39   ` Zhang, Qi Z

DPDK patches and discussions

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