From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6AF0DA04BA; Thu, 24 Sep 2020 20:02:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 122341DEE8; Thu, 24 Sep 2020 20:02:23 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id BA4421DED3 for ; Thu, 24 Sep 2020 20:02:21 +0200 (CEST) IronPort-SDR: N2Ibh0JNNo89EJHAmcLWq0kJfoUfb9im9NfDL6PxTzH3zNrzWdgo1NtFmhMMTwGRRtBO9iBpCP q53NkqVJIhUA== X-IronPort-AV: E=McAfee;i="6000,8403,9754"; a="140729661" X-IronPort-AV: E=Sophos;i="5.77,298,1596524400"; d="scan'208";a="140729661" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2020 11:02:20 -0700 IronPort-SDR: BU+DLpsL+oGICOON9A6i7O5OPejf50njB84/0/ecenPcoL7coxASifFkuKvO963ViX5tQHJCxf Z78WCw0T0Upw== X-IronPort-AV: E=Sophos;i="5.77,298,1596524400"; d="scan'208";a="512268406" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.251.85.112]) ([10.251.85.112]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2020 11:02:19 -0700 To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= , dev Cc: "Wang, Zhihong" , "Xia, Chenbo" , Maxime Coquelin , Anatoly Burakov , David Marchand , Gaetan Rivet References: <19840b6a-b08f-4877-a530-15ced259bedf.huawei.xhw@alibaba-inc.com> <3f5bd3a2-8696-237d-2723-35be5a60bb65@alibaba-inc.com> From: Ferruh Yigit Message-ID: <6b99b215-df24-10d8-5b10-75848e89e572@intel.com> Date: Thu, 24 Sep 2020 19:02:15 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: <3f5bd3a2-8696-237d-2723-35be5a60bb65@alibaba-inc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH] pci: support both PIO and MMIO BAR for legacy virtio on x86 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 9/15/2020 4:21 PM, 谢华伟(此时此刻) wrote: > Hi Ferruh: > Legacy virtio only supports PIO BAR resource. As we need to create lots > of virtio devices and PIO resource on x86 is very limited, we expose > MMIO BAR. > Kernel support both PIO and MMIO BAR for legacy virtio device. This > patch deals with two cases in the similar way. > Thanks Huawei, I was about to ask the actual motivation for the patch, better to put this explenation into the commit log. If legacy virtio device only supports PIO BAR, how exposing MMIO BAR helps? Or if there is MMIO BAR available in the device, why not mapping them instead of using PIO? Most probably I am missing something but can you please help to understand. Also below code unifies vfio & uio cases for PIO into same function. Are you using igb_uio or both? I am not sure about unifiying the vfio case, what do you think not touching that case in this patch? There are a few more comments inline, please check. Btw, the patch doesn't apply cleanly, can you please send a new version on top of latest head of repo? > On 2020/9/15 16:18, 谢华伟(此时此刻) wrote: >>  From d0138f24037d8df14cac04c2c24831e4b5d27b8c Mon Sep 17 00:00:00 2001 >> From: "huawei.xhw" >> Date: Mon, 14 Sep 2020 23:44:56 +0800 >> Subject: [PATCH] pci:  support both PIO and MMIO BAR for legacy virtio >> on x86 >> >> In previous implementation, with igb_uio we get PIO address from igb_uio >> sysfs entry; with uio_pci_generic, we get PIO address from >> /proc/ioports. >> For PIO/MMIO RW, there is different path for different drivers and arch. >> For VFIO, PIO/MMIO RW is through syscall, which has big performance >> issue. >> On X86, it assumes only PIO is supported. >> >> This is too much twisted. >> This patch unifies the way to get both PIO and MMIO address for >> different driver >> and arch, all from standard resource attr under pci sysfs. >> >> We distinguish PIO and MMIO by their address. It is ugly but works. >> >> Signed-off-by: huawei.xhw <...> >> --- a/drivers/bus/pci/linux/pci_uio.c >> +++ b/drivers/bus/pci/linux/pci_uio.c >> @@ -372,52 +372,82 @@ >>   pci_uio_ioport_map(struct rte_pci_device *dev, int bar, >>              struct rte_pci_ioport *p) >>   { There are two 'pci_uio_ioport_map()', one for x86 and other for rest. This one is for x86, since read/write functions for multiple arch combined together, should non-x86 version of this function updated or removed completely? <...> >> +    if (flags & IORESOURCE_IO) { >> +        iobar = 1; >> +        base = (unsigned long)phys_addr; >> +        RTE_LOG(INFO, EAL, "%s(): PIO BAR %08lx detected\n", >> __func__, base); >> +    } else if (flags & IORESOURCE_MEM) { >> +        iobar = 0; >> +        base = (unsigned long)dev->mem_resource[bar].addr; Isn't the 'mem_resource[bar].addr' value set only when it is mapped? For this case I guess it will be 0x0. If not who maps it first? >> +        RTE_LOG(INFO, EAL, "%s(): MMIO BAR %08lx detected\n", >> __func__, base); >> +    } else { >> +        RTE_LOG(ERR, EAL, "%s(): unknown BAR type\n", __func__); >> +        goto error; >> +    } >> + >> +    if (iobar && rte_eal_iopl_init() != 0) { >> +        RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for >> PCI device %s\n", >> +            __func__, dev->name); >> +        goto error; >>       } >> -    /* ensure we don't get anything funny here, read/write will cast to >> -     * uin16_t */ >> -    if (start > UINT16_MAX) >> -        return -1; >>       /* FIXME only for primary process ? */ >>       if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) { >> +        uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0); >> +        if (uio_num < 0) >> +            goto error; How this will work with vfio?