From: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
To: dev@dpdk.org
Cc: Kumar Sanghvi <kumaras@chelsio.com>,
Nirranjan Kirubaharan <nirranjan@chelsio.com>
Subject: [dpdk-dev] [PATCH 3/5] cxgbe: set default PCIe completion timeout
Date: Fri, 6 May 2016 13:13:17 +0530 [thread overview]
Message-ID: <6ccc539bdeb263ab1160d2f39771a0e9fa6c3ce3.1462519635.git.rahul.lakkireddy@chelsio.com> (raw)
In-Reply-To: <cover.1462519635.git.rahul.lakkireddy@chelsio.com>
In-Reply-To: <cover.1462519635.git.rahul.lakkireddy@chelsio.com>
Program the PCIe completion timeout to 4 sec to give enough time
to allow completions to be received successfully in some older systems.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
---
drivers/net/cxgbe/base/adapter.h | 2 ++
drivers/net/cxgbe/base/t4_hw.c | 19 ++++++++++++++++++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h
index af34721..73e7aca 100644
--- a/drivers/net/cxgbe/base/adapter.h
+++ b/drivers/net/cxgbe/base/adapter.h
@@ -431,8 +431,10 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_CAPABILITY_LIST 0x34
/* Offset of first capability list entry */
+#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
+#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
/**
* t4_os_pci_write_cfg4 - 32-bit write to PCI config space
diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c
index 79af806..7882f9a 100644
--- a/drivers/net/cxgbe/base/t4_hw.c
+++ b/drivers/net/cxgbe/base/t4_hw.c
@@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
- * Copyright(c) 2014-2015 Chelsio Communications.
+ * Copyright(c) 2014-2016 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -2326,6 +2326,21 @@ int t4_get_flash_params(struct adapter *adapter)
return 0;
}
+static void set_pcie_completion_timeout(struct adapter *adapter,
+ u8 range)
+{
+ u32 pcie_cap;
+ u16 val;
+
+ pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
+ if (pcie_cap) {
+ t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
+ val &= 0xfff0;
+ val |= range;
+ t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
+ }
+}
+
/**
* t4_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
@@ -2384,6 +2399,8 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.portvec = 1;
adapter->params.vpd.cclk = 50000;
+ /* Set pci completion timeout value to 4 seconds. */
+ set_pcie_completion_timeout(adapter, 0xd);
return 0;
}
--
2.5.3
next prev parent reply other threads:[~2016-05-06 7:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-06 7:43 [dpdk-dev] [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy
2016-05-06 7:43 ` [dpdk-dev] [PATCH 1/5] pci: fix access to PCI config space in bsd Rahul Lakkireddy
2016-05-31 16:20 ` Bruce Richardson
2016-06-01 8:34 ` Rahul Lakkireddy
2016-05-06 7:43 ` [dpdk-dev] [PATCH 2/5] cxgbe: add support to access PCI config space Rahul Lakkireddy
2016-05-06 7:43 ` Rahul Lakkireddy [this message]
2016-05-06 7:43 ` [dpdk-dev] [PATCH 4/5] cxgbe: add support to get/set EEPROM Rahul Lakkireddy
2016-05-06 7:43 ` [dpdk-dev] [PATCH 5/5] cxgbe: add support to get register dump Rahul Lakkireddy
2016-06-02 14:43 ` [dpdk-dev] [PATCH 0/5] cxgbe: add features to CXGBE PMD Bruce Richardson
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