From: "Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco)" <jgrajcia@cisco.com>
To: "Phil Yang (Arm Technology China)" <Phil.Yang@arm.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: "thomas@monjalon.net" <thomas@monjalon.net>,
"jerinj@marvell.com" <jerinj@marvell.com>,
Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
"Damjan Marion (damarion)" <damarion@cisco.com>, nd <nd@arm.com>,
"Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>,
"ferruh.yigit@intel.com" <ferruh.yigit@intel.com>,
nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way barrier
Date: Wed, 9 Oct 2019 11:17:14 +0000 [thread overview]
Message-ID: <6d11f6f6cb1440878a1f2d527576cca6@XCH-ALN-004.cisco.com> (raw)
In-Reply-To: <VE1PR08MB46403AB4A9A76F71ECBB05C8E9950@VE1PR08MB4640.eurprd08.prod.outlook.com>
> > > > -----Original Message-----
> > > > From: dev <dev-bounces@dpdk.org> On Behalf Of Phil Yang
> > > > Sent: Monday, August 26, 2019 7:00 PM
> > > > To: jgrajcia@cisco.com; dev@dpdk.org
> > > > Cc: thomas@monjalon.net; jerinj@marvell.com; Honnappa Nagarahalli
> > > > <Honnappa.Nagarahalli@arm.com>; damarion@cisco.com; nd
> > > <nd@arm.com>
> > > > Subject: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way
> > > > barrier
> > > >
> > > > Using 'rte_mb' to synchronize the shared ring head/tail between
> > > > producer and consumer will stall the pipeline and damage
> > > > performance on the weak memory model platforms, such like aarch64.
> > > > Meanwhile update the shared ring head and tail are observable and
> > > > ordered
> > between
> > > CPUs on IA.
> > > >
> > > > Optimized this full barrier with the one-way barrier can improve
> > > > the throughput. On aarch64 n1sdp server this patch make testpmd
> > throughput
> > > > boost 2.1%. On Intel E5-2640, testpmd got 3.98% performance gain.
> > > >
> > > > Signed-off-by: Phil Yang <phil.yang@arm.com>
> > > > Reviewed-by: Gavin Hu <gavin.hu@arm.com>
> >
> > The patch is looking good, but 'MEMIF_VERSION_MAJOR' in memif.h needs
> > to be set to 3 as ring pointers are no longer volatile.
>
> Updated in v2.
> Thanks for your comments.
>
> Thanks,
> Phil
I jumped the gun with the version bump. The change doesn't break compatibility. I'm putting reviewed label on v1.
Sorry for the inconvenience.
Reviewed-by: Jakub Grajciar <jgrajcia@cisco.com>
next prev parent reply other threads:[~2019-10-09 11:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-26 11:00 Phil Yang
2019-08-26 11:03 ` Phil Yang (Arm Technology China)
2019-10-08 11:05 ` Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco)
2019-10-09 2:10 ` Phil Yang (Arm Technology China)
2019-10-09 11:17 ` Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco) [this message]
2019-10-14 8:59 ` Ferruh Yigit
2019-10-09 2:04 ` [dpdk-dev] [PATCH v2] " Phil Yang
2019-10-09 11:14 ` Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco)
2019-10-10 14:04 ` David Marchand
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