From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD81FA0C45; Wed, 22 Sep 2021 10:08:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66CD541196; Wed, 22 Sep 2021 10:08:37 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id B03D04069E for ; Wed, 22 Sep 2021 10:08:35 +0200 (CEST) Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4HDrRV0rxtzRRXh; Wed, 22 Sep 2021 16:04:22 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Wed, 22 Sep 2021 16:08:33 +0800 Received: from [10.40.190.165] (10.40.190.165) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Wed, 22 Sep 2021 16:08:33 +0800 To: Conor Walsh , , , CC: References: <20210827172550.1522362-1-conor.walsh@intel.com> <20210917154227.737554-1-conor.walsh@intel.com> <20210917154227.737554-5-conor.walsh@intel.com> From: fengchengwen Message-ID: <6d4f6b80-a546-0e6e-418f-1c26f4b3bd92@huawei.com> Date: Wed, 22 Sep 2021 16:08:33 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20210917154227.737554-5-conor.walsh@intel.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.40.190.165] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH v4 04/11] dma/ioat: add configuration functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2021/9/17 23:42, Conor Walsh wrote: > Add functions for device configuration. The info_get and close functions > are included here also. info_get can be useful for checking successful > configuration and close is used by the dmadev api when releasing a > configured device. > > Signed-off-by: Conor Walsh > Reviewed-by: Kevin Laatz > --- > doc/guides/dmadevs/ioat.rst | 24 +++++++++ > drivers/dma/ioat/ioat_dmadev.c | 93 ++++++++++++++++++++++++++++++++++ > 2 files changed, 117 insertions(+) > > diff --git a/doc/guides/dmadevs/ioat.rst b/doc/guides/dmadevs/ioat.rst > index 45a2e65d70..6092599fe4 100644 > --- a/doc/guides/dmadevs/ioat.rst > +++ b/doc/guides/dmadevs/ioat.rst > @@ -62,3 +62,27 @@ For example:: > Once probed successfully, the device will appear as a ``dmadev``, that is a > "DMA device type" inside DPDK, and can be accessed using APIs from the > ``rte_dmadev`` library. > + > +Device Configuration > +~~~~~~~~~~~~~~~~~~~~~ > + > +Configuring an IOAT dmadev device is done using the ``rte_dma_configure()`` > +and ``rte_dma_vchan_setup()`` APIs. ``rte_dma_configure()`` uses the structure > +``rte_dma_conf`` to configure an IOAT device, within this struct the number > +of virtual DMA channels for the device is set and silent mode can be enabled. > +Each IOAT device can only use 1 virtual DMA channel and silent mode is not > +supported so these will always be set to ``1`` and ``false``. > +``rte_dma_vchan_setup()`` uses the structure ``rte_dma_vchan_conf`` to setup > +a virtual DMA channel within this struct the transfer direction and ring size > +are set. Generally for an onboard Intel\ |reg| IOAT device the transfer direction > +will be set to ``RTE_DMA_DIR_MEM_TO_MEM`` to copy from memory to memory (more info > +available in the dmadev API guide). The ring size must be a power of two, between > +64 and 4096. > + > +The following code shows how the device is configured in ``test_dmadev.c``: > + > +.. literalinclude:: ../../../app/test/test_dmadev.c > + :language: c > + :start-after: Setup of the dmadev device. 8< > + :end-before: >8 End of setup of the dmadev device. > + :dedent: 1 > diff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c > index 370be3ec72..d58022e258 100644 > --- a/drivers/dma/ioat/ioat_dmadev.c > +++ b/drivers/dma/ioat/ioat_dmadev.c > @@ -12,9 +12,98 @@ static struct rte_pci_driver ioat_pmd_drv; > > RTE_LOG_REGISTER_DEFAULT(ioat_pmd_logtype, INFO); > > +#define DESC_SZ sizeof(struct ioat_dma_hw_desc) > + > #define IOAT_PMD_NAME dmadev_ioat > #define IOAT_PMD_NAME_STR RTE_STR(IOAT_PMD_NAME) > > +/* Configure a device. */ > +static int > +ioat_dev_configure(struct rte_dma_dev *dev __rte_unused, const struct rte_dma_conf *dev_conf, > + uint32_t conf_sz) > +{ > + if (sizeof(struct rte_dma_conf) != conf_sz) > + return -EINVAL; > + > + if (dev_conf->nb_vchans != 1) > + return -EINVAL; > + > + return 0; > +} > + > +/* Setup a virtual channel for IOAT, only 1 vchan is supported. */ > +static int > +ioat_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan __rte_unused, > + const struct rte_dma_vchan_conf *qconf, uint32_t qconf_sz) > +{ > + struct ioat_dmadev *ioat = dev->dev_private; > + uint16_t max_desc = qconf->nb_desc; > + int i; > + > + if (sizeof(struct rte_dma_vchan_conf) != qconf_sz) > + return -EINVAL; > + > + ioat->qcfg = *qconf; > + > + if (!rte_is_power_of_2(max_desc)) { > + max_desc = rte_align32pow2(max_desc); > + IOAT_PMD_DEBUG("DMA dev %u using %u descriptors", dev->data->dev_id, max_desc); > + ioat->qcfg.nb_desc = max_desc; > + } > + > + /* In case we are reconfiguring a device, free any existing memory. */ > + rte_free(ioat->desc_ring); > + > + ioat->desc_ring = rte_zmalloc(NULL, sizeof(*ioat->desc_ring) * max_desc, 0); > + if (ioat->desc_ring == NULL) > + return -ENOMEM; > + > + ioat->ring_addr = rte_mem_virt2iova(ioat->desc_ring); > + > + ioat->status_addr = rte_mem_virt2iova(ioat) + offsetof(struct ioat_dmadev, status); > + > + /* Ensure all counters are reset, if reconfiguring/restarting device. */ > + ioat->next_read = 0; > + ioat->next_write = 0; > + ioat->last_write = 0; > + ioat->offset = 0; > + ioat->failure = 0; > + > + /* Configure descriptor ring - each one points to next. */ > + for (i = 0; i < ioat->qcfg.nb_desc; i++) { > + ioat->desc_ring[i].next = ioat->ring_addr + > + (((i + 1) % ioat->qcfg.nb_desc) * DESC_SZ); > + } > + > + return 0; > +} > + > +/* Get device information of a device. */ > +static int > +ioat_dev_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *info, uint32_t size) > +{ > + struct ioat_dmadev *ioat = dev->dev_private; > + > + if (size < sizeof(*info)) > + return -EINVAL; > + info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | > + RTE_DMA_CAPA_OPS_COPY | > + RTE_DMA_CAPA_OPS_FILL; > + info->max_vchans = 1; > + info->min_desc = 32; > + info->max_desc = 4096; > + info->nb_vchans = (ioat->desc_ring == NULL); The nb_vchans will overwrite by library. > + return 0; > +} > + > +/* Close a configured device. */ > +static int > +ioat_dev_close(struct rte_dma_dev *dev) > +{ > + RTE_SET_USED(dev); > + return 0; > +} > + > /* Dump DMA device info. */ > static int > ioat_dev_dump(const struct rte_dma_dev *dev, FILE *f) > @@ -77,7 +166,11 @@ static int > ioat_dmadev_create(const char *name, struct rte_pci_device *dev) > { > static const struct rte_dma_dev_ops ioat_dmadev_ops = { > + .dev_close = ioat_dev_close, > + .dev_configure = ioat_dev_configure, > .dev_dump = ioat_dev_dump, > + .dev_info_get = ioat_dev_info_get, > + .vchan_setup = ioat_vchan_setup, > }; > > struct rte_dma_dev *dmadev = NULL; >