From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id 6FE941B8FA; Fri, 14 Dec 2018 18:04:25 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AAB2989AF4; Fri, 14 Dec 2018 17:04:24 +0000 (UTC) Received: from ktraynor.remote.csb (ovpn-116-106.ams2.redhat.com [10.36.116.106]) by smtp.corp.redhat.com (Postfix) with ESMTP id DFBFC1054FDD; Fri, 14 Dec 2018 17:04:22 +0000 (UTC) To: "Zhang, Qi Z" , "Zhao1, Wei" , "Player, Timmons" , "stable@dpdk.org" Cc: "dev@dpdk.org" , "Lu, Wenzhuo" References: <20181119144833.7732-1-timmons.player@spirent.com> <039ED4275CED7440929022BC67E70611532E87A4@SHSMSX103.ccr.corp.intel.com> From: Kevin Traynor Organization: Red Hat Message-ID: <6d757bc2-b00e-c3ce-556c-d799caa58f7d@redhat.com> Date: Fri, 14 Dec 2018 17:04:21 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: <039ED4275CED7440929022BC67E70611532E87A4@SHSMSX103.ccr.corp.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 14 Dec 2018 17:04:24 +0000 (UTC) Subject: Re: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using MSI-X X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Dec 2018 17:04:25 -0000 On 11/20/2018 04:16 AM, Zhang, Qi Z wrote: > > >> -----Original Message----- >> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zhao1, Wei >> Sent: Monday, November 19, 2018 7:29 PM >> To: Player, Timmons >> Cc: dev@dpdk.org; Lu, Wenzhuo >> Subject: Re: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using MSI-X >> >> Acked-by: Wei Zhao > > Applied to dpdk-next-net-intel. > This has stable tag and but no Fixes tag. Which stable branch is it relevant for? > Thanks > Qi >> >>> -----Original Message----- >>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Player, Timmons >>> Sent: Monday, November 19, 2018 10:49 PM >>> To: Lu, Wenzhuo >>> Cc: dev@dpdk.org; Player, Timmons >>> Subject: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using >>> MSI-X >>> >>> Take the 'other interrupt' into account when setting up MSI-X >>> interrupts and use the proper mask when enabling it. >>> Also, rearm the MSI-X vector after the LSC interrupt fires. >>> >>> This change allows both LSC and RXQ interrupts to work at the same >>> time when using MSI-X interrupts. >>> >>> Signed-off-by: Timmons C. Player >>> --- >>> v2: >>> * Update igb_intr_{enable,disable} to only touch the 'other interrupt' >>> when it is explicitly enabled. >>> >>> drivers/net/e1000/igb_ethdev.c | 43 +++++++++++++++++++++++++++++- >>> ---- >>> 1 file changed, 37 insertions(+), 6 deletions(-) >>> >>> diff --git a/drivers/net/e1000/igb_ethdev.c >>> b/drivers/net/e1000/igb_ethdev.c index d9d29d22f..87c9aedf2 100644 >>> --- a/drivers/net/e1000/igb_ethdev.c >>> +++ b/drivers/net/e1000/igb_ethdev.c >>> @@ -68,6 +68,9 @@ >>> #define E1000_VET_VET_EXT 0xFFFF0000 >>> #define E1000_VET_VET_EXT_SHIFT 16 >>> >>> +/* MSI-X other interrupt vector */ >>> +#define IGB_MSIX_OTHER_INTR_VEC 0 >>> + >>> static int eth_igb_configure(struct rte_eth_dev *dev); static int >>> eth_igb_start(struct rte_eth_dev *dev); static void >>> eth_igb_stop(struct rte_eth_dev *dev); @@ -138,7 +141,7 @@ static void >>> igb_vlan_hw_extend_disable(struct rte_eth_dev *dev); static int >>> eth_igb_led_on(struct rte_eth_dev *dev); static int >>> eth_igb_led_off(struct rte_eth_dev *dev); >>> >>> -static void igb_intr_disable(struct e1000_hw *hw); >>> +static void igb_intr_disable(struct rte_eth_dev *dev); >>> static int igb_get_rx_buffer_size(struct e1000_hw *hw); static int >>> eth_igb_rar_set(struct rte_eth_dev *dev, >>> struct ether_addr *mac_addr, >>> @@ -538,14 +541,31 @@ igb_intr_enable(struct rte_eth_dev *dev) >>> E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); >>> struct e1000_hw *hw = >>> E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); >>> + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); >>> + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; >>> + >>> + if (rte_intr_allow_others(intr_handle) && >>> + dev->data->dev_conf.intr_conf.lsc != 0) { >>> + E1000_WRITE_REG(hw, E1000_EIMS, 1 << >>> IGB_MSIX_OTHER_INTR_VEC); >>> + } >>> >>> E1000_WRITE_REG(hw, E1000_IMS, intr->mask); >>> E1000_WRITE_FLUSH(hw); >>> } >>> >>> static void >>> -igb_intr_disable(struct e1000_hw *hw) >>> +igb_intr_disable(struct rte_eth_dev *dev) >>> { >>> + struct e1000_hw *hw = >>> + E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); >>> + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); >>> + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; >>> + >>> + if (rte_intr_allow_others(intr_handle) && >>> + dev->data->dev_conf.intr_conf.lsc != 0) { >>> + E1000_WRITE_REG(hw, E1000_EIMC, 1 << >>> IGB_MSIX_OTHER_INTR_VEC); >>> + } >>> + >>> E1000_WRITE_REG(hw, E1000_IMC, ~0); >>> E1000_WRITE_FLUSH(hw); >>> } >>> @@ -1486,7 +1506,7 @@ eth_igb_stop(struct rte_eth_dev *dev) >>> >>> eth_igb_rxtx_control(dev, false); >>> >>> - igb_intr_disable(hw); >>> + igb_intr_disable(dev); >>> >>> /* disable intr eventfd mapping */ >>> rte_intr_disable(intr_handle); >>> @@ -2768,12 +2788,15 @@ static int eth_igb_rxq_interrupt_setup(struct >>> rte_eth_dev *dev) >>> uint32_t mask, regval; >>> struct e1000_hw *hw = >>> E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); >>> + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); >>> + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; >>> + int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0; >>> struct rte_eth_dev_info dev_info; >>> >>> memset(&dev_info, 0, sizeof(dev_info)); >>> eth_igb_infos_get(dev, &dev_info); >>> >>> - mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); >>> + mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << >>> misc_shift; >>> regval = E1000_READ_REG(hw, E1000_EIMS); >>> E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); >>> >>> @@ -2800,7 +2823,7 @@ eth_igb_interrupt_get_status(struct rte_eth_dev >>> *dev) >>> struct e1000_interrupt *intr = >>> E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); >>> >>> - igb_intr_disable(hw); >>> + igb_intr_disable(dev); >>> >>> /* read-on-clear nic registers here */ >>> icr = E1000_READ_REG(hw, E1000_ICR); @@ -5583,13 +5606,17 @@ >>> eth_igb_configure_msix_intr(struct rte_eth_dev >>> *dev) >>> E1000_GPIE_NSICR); >>> intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << >>> misc_shift; >>> + >>> + if (dev->data->dev_conf.intr_conf.lsc != 0) >>> + intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC); >>> + >>> regval = E1000_READ_REG(hw, E1000_EIAC); >>> E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); >>> >>> /* enable msix_other interrupt */ >>> regval = E1000_READ_REG(hw, E1000_EIMS); >>> E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); >>> - tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) >>> << 8; >>> + tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) >>> << 8; >>> E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); >>> } >>> >>> @@ -5598,6 +5625,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev >>> *dev) >>> */ >>> intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << >>> misc_shift; >>> + >>> + if (dev->data->dev_conf.intr_conf.lsc != 0) >>> + intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC); >>> + >>> regval = E1000_READ_REG(hw, E1000_EIAM); >>> E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); >>> >>> -- >>> 2.17.1 >