From: "Juraj Linkeš" <juraj.linkes@pantheon.tech>
To: Rahul Bhansali <rbhansali@marvell.com>,
"dev@dpdk.org" <dev@dpdk.org>,
Ruifeng Wang <ruifeng.wang@arm.com>,
Jan Viktorin <viktorin@rehivetech.com>,
Bruce Richardson <bruce.richardson@intel.com>
Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Subject: RE: [PATCH v4 1/2] config/arm: add SVE ACLE control flag
Date: Wed, 18 May 2022 14:45:09 +0000 [thread overview]
Message-ID: <717ed4ff512e480a84aac7dea7a1d9a8@pantheon.tech> (raw)
In-Reply-To: <CO6PR18MB384415531FA857C3F4B87156B8D19@CO6PR18MB3844.namprd18.prod.outlook.com>
> > > -----Original Message-----
> > > From: Rahul Bhansali <rbhansali@marvell.com>
> > > Sent: Monday, May 9, 2022 12:20 PM
> > > To: dev@dpdk.org; Ruifeng Wang <ruifeng.wang@arm.com>; Jan Viktorin
> > > <viktorin@rehivetech.com>; Bruce Richardson
> > > <bruce.richardson@intel.com>
> > > Cc: jerinj@marvell.com; Rahul Bhansali <rbhansali@marvell.com>
> > > Subject: [PATCH v4 1/2] config/arm: add SVE ACLE control flag
> > >
> > > This add the control flag for SVE ACLE to enable or disable
> > > RTE_HAS_SVE_ACLE macro in the build.
> > >
> > > Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> > > ---
> > > Changes in v4:
> > > - Resend patches. With v3, patches were not sent properly in single series.
> > >
> > > Changes in v3:
> > > - Moved sve_acle condition to be consider for RTE_HAS_SVE_ACLE flag only.
> > >
> > > Changes in v2:
> > > - Renamed the flag to sve_acle from sve
> > > - Added double-indent.
> > >
> > > config/arm/meson.build | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > 8aead74086..6f8961eac8 100644
> > > --- a/config/arm/meson.build
> > > +++ b/config/arm/meson.build
> > > @@ -605,7 +605,7 @@ endif
> > >
> > > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> > > compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
> > > - if (cc.check_header('arm_sve.h'))
> > > + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle',
> > > + true))
> >
> > This configuration will be applied only for non-native builds - when
> > we specify either -Dplatform or do a cross-build (with the target
> > being cn10k). Is that what we want? I'm not sure how we'd do that for
> > native builds that won't affect non- cn10k builds, as we can do this
> > either at the implementer or part number level (both of which cover other
> SoCs).
> >
>
> For native build, we will need to specify -Dplatform for cn10k so that sve_acle
> can be disabled for this only. Currently performance impact of SVE_ACLE vs
> Neon is checked on cn10k only, not sure about other platforms, hence not done
> default SVE ACLE disabled for all platforms.
> For cn10k, implementor and part number is same as with N2, so not done
> required changes at that level.
>
Ok, it looks like you've thought about the native build case and have it covered.
> In future, if performance impact is same for other platforms too then we can
> have this solution based on implementor ID or part number.
>
Makes sense, as I suspected we can't do this change more broadly and have to use -Dplatform even for native builds.
> > > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> > > endif
> > > endif
> > > --
> > > 2.25.1
> > >
> >
>
Reviewed-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
next prev parent reply other threads:[~2022-05-18 14:45 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 14:27 [PATCH 1/2] config/arm: add SVE " Rahul Bhansali
2022-05-05 14:27 ` [PATCH 2/2] config/arm: disable SVE for cn10k Rahul Bhansali
2022-05-06 2:29 ` fengchengwen
2022-05-06 4:54 ` [EXT] " Rahul Bhansali
2022-05-06 6:36 ` fengchengwen
2022-05-06 7:23 ` Ruifeng Wang
2022-05-06 13:17 ` Rahul Bhansali
2022-05-07 0:52 ` fengchengwen
2022-05-05 14:39 ` [PATCH 1/2] config/arm: add SVE control flag Bruce Richardson
2022-05-06 14:16 ` [EXT] " Rahul Bhansali
2022-05-06 2:23 ` fengchengwen
2022-05-07 9:39 ` [PATCH v2 1/2] config/arm: add SVE ACLE " Rahul Bhansali
2022-05-07 9:39 ` [PATCH v2 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-09 0:49 ` [PATCH v2 1/2] config/arm: add SVE ACLE control flag fengchengwen
2022-05-09 9:46 ` [PATCH v3 " Rahul Bhansali
2022-05-09 9:46 ` [PATCH v3 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-09 10:19 ` [PATCH v4 1/2] config/arm: add SVE ACLE control flag Rahul Bhansali
2022-05-09 10:19 ` [PATCH v4 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-10 2:57 ` fengchengwen
2022-05-11 1:35 ` Ruifeng Wang
2022-05-11 4:12 ` Honnappa Nagarahalli
2022-05-10 2:57 ` [PATCH v4 1/2] config/arm: add SVE ACLE control flag fengchengwen
2022-05-11 1:35 ` Ruifeng Wang
2022-05-11 4:09 ` Honnappa Nagarahalli
2022-05-17 7:56 ` Juraj Linkeš
2022-05-18 9:18 ` Rahul Bhansali
2022-05-18 14:45 ` Juraj Linkeš [this message]
2022-05-19 13:28 ` [PATCH v5 " Rahul Bhansali
2022-05-19 13:28 ` [PATCH v5 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-06-01 22:38 ` Thomas Monjalon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=717ed4ff512e480a84aac7dea7a1d9a8@pantheon.tech \
--to=juraj.linkes@pantheon.tech \
--cc=bruce.richardson@intel.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=rbhansali@marvell.com \
--cc=ruifeng.wang@arm.com \
--cc=viktorin@rehivetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).