From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A830CA0503; Wed, 18 May 2022 16:45:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51DC140156; Wed, 18 May 2022 16:45:13 +0200 (CEST) Received: from mailgw02.pantheon.sk (mailgw01.pantheon.sk [46.229.239.26]) by mails.dpdk.org (Postfix) with ESMTP id 2A73F400D6 for ; Wed, 18 May 2022 16:45:12 +0200 (CEST) Received: from mailgw02.pantheon.sk (localhost.localdomain [127.0.0.1]) by mailgw02.pantheon.sk (Proxmox) with ESMTP id E3BCD182DB1; Wed, 18 May 2022 16:45:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pantheon.tech; h=cc:cc:content-transfer-encoding:content-type:content-type :date:from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=dkim; bh=th0B0v4A9LByhAS6lgVA KQl8KW25YzuDiPNlFUSMBiI=; b=qUzT8zgIU7eowWZ9Om6unJW1kJ3lTk8dFvCm h4pMlwv1GTH+IlIREZ/3zCZqknCSIV8Iw0zkwHM5lPhWRdZyexWuo6uhmIEcaHKk svX23I2NhI6BvCYbq4duAXqnSZ5JbMqhsbS7dLJIFpFtTJbAwYfuiSkcyReNNqrQ LEILj2YCfJKk5cGjEB/w98D99F1AWFs4FuXDuWTCkZJ56reCs+bPvDNXu7/QtSL0 khazEbZ0BXhU0mObpjYin8/Dbs2DhydPlmhTZwaKXfkSgL9mEvGjSqcSHbu/KQ4s 38zUVpPOdzCPoauZzSOvpR25IxjuatB5pJqHlxdVK1Zly4mzSA== From: =?iso-8859-2?Q?Juraj_Linke=B9?= To: Rahul Bhansali , "dev@dpdk.org" , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: Jerin Jacob Kollanukkaran Subject: RE: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Thread-Topic: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Thread-Index: AQHYY45XK2ONfH1ELEyeiEhP4KDILK0hj6qggAK4EgCAAHuOYA== Date: Wed, 18 May 2022 14:45:09 +0000 Message-ID: <717ed4ff512e480a84aac7dea7a1d9a8@pantheon.tech> References: <20220505142744.1423344-1-rbhansali@marvell.com> <20220509101932.2403562-1-rbhansali@marvell.com> <9c1c547ea2c24bcb8c058b70ccbfe026@pantheon.tech> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.101.4.10] Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > > > -----Original Message----- > > > From: Rahul Bhansali > > > Sent: Monday, May 9, 2022 12:20 PM > > > To: dev@dpdk.org; Ruifeng Wang ; Jan Viktorin > > > ; Bruce Richardson > > > > > > Cc: jerinj@marvell.com; Rahul Bhansali > > > Subject: [PATCH v4 1/2] config/arm: add SVE ACLE control flag > > > > > > This add the control flag for SVE ACLE to enable or disable > > > RTE_HAS_SVE_ACLE macro in the build. > > > > > > Signed-off-by: Rahul Bhansali > > > --- > > > Changes in v4: > > > - Resend patches. With v3, patches were not sent properly in single s= eries. > > > > > > Changes in v3: > > > - Moved sve_acle condition to be consider for RTE_HAS_SVE_ACLE flag o= nly. > > > > > > Changes in v2: > > > - Renamed the flag to sve_acle from sve > > > - Added double-indent. > > > > > > config/arm/meson.build | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > > 8aead74086..6f8961eac8 100644 > > > --- a/config/arm/meson.build > > > +++ b/config/arm/meson.build > > > @@ -605,7 +605,7 @@ endif > > > > > > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) !=3D '' > > > compile_time_cpuflags +=3D ['RTE_CPUFLAG_SVE'] > > > - if (cc.check_header('arm_sve.h')) > > > + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', > > > + true)) > > > > This configuration will be applied only for non-native builds - when > > we specify either -Dplatform or do a cross-build (with the target > > being cn10k). Is that what we want? I'm not sure how we'd do that for > > native builds that won't affect non- cn10k builds, as we can do this > > either at the implementer or part number level (both of which cover oth= er > SoCs). > > >=20 > For native build, we will need to specify -Dplatform for cn10k so that sv= e_acle > can be disabled for this only. Currently performance impact of SVE_ACLE v= s > Neon is checked on cn10k only, not sure about other platforms, hence not = done > default SVE ACLE disabled for all platforms. > For cn10k, implementor and part number is same as with N2, so not done > required changes at that level. >=20 Ok, it looks like you've thought about the native build case and have it co= vered. > In future, if performance impact is same for other platforms too then we = can > have this solution based on implementor ID or part number. >=20 Makes sense, as I suspected we can't do this change more broadly and have t= o use -Dplatform even for native builds. > > > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) > > > endif > > > endif > > > -- > > > 2.25.1 > > > > > >=20 Reviewed-by: Juraj Linke=B9