From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2EDF5A04B5; Thu, 1 Oct 2020 12:36:34 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 05CA21DAEE; Thu, 1 Oct 2020 12:22:09 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id AF99E1DAE5 for ; Thu, 1 Oct 2020 12:22:06 +0200 (CEST) IronPort-SDR: 54W431hRrLODCZYw5u8EbTTBawz6KtRb7JR0Q7B1v0xjvafPIa+eagDinTH+E29AW800eewt6F b13dOo+9d1Pg== X-IronPort-AV: E=McAfee;i="6000,8403,9760"; a="180840100" X-IronPort-AV: E=Sophos;i="5.77,323,1596524400"; d="scan'208";a="180840100" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2020 03:22:04 -0700 IronPort-SDR: ivajEtxIv6Zgdm2mWUl/KDpPtm687flkyWIorLNUMw56j0crdslaGjYAB4lvxweipHbKySxKxN SydwipaB+K/w== X-IronPort-AV: E=Sophos;i="5.77,323,1596524400"; d="scan'208";a="458064470" Received: from aburakov-mobl.ger.corp.intel.com (HELO [10.213.194.116]) ([10.213.194.116]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2020 03:22:02 -0700 To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= , dev , "ferruh.yigit" Cc: Maxime Coquelin , David Marchand , "Wang, Zhihong" , "Xia, Chenbo" , Gaetan Rivet , =?UTF-8?B?5p2o6IiqKOihjOWuqik=?= References: <68ecd941-9c56-4de7-fae2-2ad15bdfd81a@alibaba-inc.com> From: "Burakov, Anatoly" Message-ID: <719c243a-2ff9-ba6e-e587-e638f8e16bfa@intel.com> Date: Thu, 1 Oct 2020 11:22:00 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <68ecd941-9c56-4de7-fae2-2ad15bdfd81a@alibaba-inc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v2] pci: support both PIO and MMIO BAR for legacy virtio on x86 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 30-Sep-20 3:59 PM, 谢华伟(此时此刻） wrote: > From c13f981e287254cd0877cc7b98ee2dd7b80c3b69 Mon Sep 17 00:00:00 2001 > From: "huawei.xhw" > Date: Wed, 30 Sep 2020 22:37:03 +0800 > Subject: [PATCH v2] pci:  support both PIO and MMIO BAR for legacy > virtio on >  x86 > > Legacy virtio-pci only supports PIO BAR resource. As we need to create > lots of > virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR. > > Kernel supports both PIO  and MMIO BAR for legacy virtio-pci device. We > handles > different type of BAR in the similar way. > > In previous implementation, with igb_uio we get PIO address from igb_uio > sysfs entry; with uio_pci_generic, we get PIO address from > /proc/ioports. > For PIO/MMIO RW, there is different path for different drivers and arch. > For VFIO, PIO/MMIO RW is through syscall, which has big performance > issue. > On X86, it assumes only PIO is supported. > > All of the above is too much twisted. > This patch unifies the way to get both PIO and MMIO address for > different driver > and arch, all from standard resource attr under pci sysfs. > > We distinguish PIO and MMIO by their address like how kernel does. It is > ugly but works. > > Signed-off-by: huawei.xhw > --- You patches are somehow malformed (at least according to my inline diff viewer). Are you using git-send-email to send patches? -- Thanks, Anatoly