From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B76BFA0547; Wed, 19 May 2021 17:02:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3616640041; Wed, 19 May 2021 17:02:36 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id A1DD94003F for ; Wed, 19 May 2021 17:02:33 +0200 (CEST) IronPort-SDR: zg4VyykLzVaUk3n10+iwj24EGVOhTel3zqPcvKLYUsM1tusYveZsGHe88621QU4Vi3NjLtKQ+a saneoEZG60dw== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="197905355" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="197905355" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 08:02:32 -0700 IronPort-SDR: pcytNnl1L6F2Xqcwyo3E2vkqHSvYdZW6Wmk5zW+edyIbelFpXl/2hAlfvVMH8q8JW9jLCrMX55 n+NRxovhP/YA== X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="411769523" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.224.148]) ([10.213.224.148]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 08:02:29 -0700 To: Chengwen Feng , thomas@monjalon.net Cc: dev@dpdk.org, jerinj@marvell.com, ruifeng.wang@arm.com, viktorin@rehivetech.com, bruce.richardson@intel.com, Honnappa.Nagarahalli@arm.com, jerinjacobk@gmail.com, juraj.linkes@pantheon.tech, nd@arm.com References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1621430731-27753-1-git-send-email-fengchengwen@huawei.com> <1621430731-27753-3-git-send-email-fengchengwen@huawei.com> From: Ferruh Yigit X-User: ferruhy Message-ID: <73ffa983-e44b-a7d2-456c-f010db0d5c48@intel.com> Date: Wed, 19 May 2021 16:02:25 +0100 MIME-Version: 1.0 In-Reply-To: <1621430731-27753-3-git-send-email-fengchengwen@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v6 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 5/19/2021 2:25 PM, Chengwen Feng wrote: > Currently, the SVE code is compiled only when -march supports SVE > (e.g. '-march=armv8.2a+sve'), there maybe some problem[1] with this > approach. > > The solution: > a. If the minimum instruction set support SVE then compiles it. > b. Else if the compiler support SVE then compiles it. > c. Otherwise don't compile it. > > [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html > > Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") > Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") > Cc: stable@dpdk.org > > Signed-off-by: Chengwen Feng The patch passes the CI build [1], but in that test sve file is not compiled at all because of missing header file [2]. I wonder if the warning caused by conflicting switch [3] is still valid, we need a platform that sve file is compiled to verify this. Do you have this environment, that sets '-mcpu=armv8.1-a'. Btw, CI reports unit test failure, I don't think it is related with this patch but can you please double check? [1] https://lab.dpdk.org/results/dashboard/patchsets/17135/ [2] Check usable header "arm_sve.h" : NO [3] error: switch ‘-mcpu=armv8.1-a’ conflicts with ‘-march=armv8.2-a’ switch [-Werror] > --- > drivers/net/hns3/hns3_rxtx.c | 2 +- > drivers/net/hns3/meson.build | 21 ++++++++++++++++++++- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c > index 1d7a769..4ef20c6 100644 > --- a/drivers/net/hns3/hns3_rxtx.c > +++ b/drivers/net/hns3/hns3_rxtx.c > @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) > static bool > hns3_get_sve_support(void) > { > -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) > +#if defined(CC_SVE_SUPPORT) > if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) > return false; > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) > diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build > index 53c7df7..5f9af9b 100644 > --- a/drivers/net/hns3/meson.build > +++ b/drivers/net/hns3/meson.build > @@ -35,7 +35,26 @@ deps += ['hash'] > > if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') > sources += files('hns3_rxtx_vec.c') > - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' > + > + # compile SVE when: > + # a. support SVE in minimum instruction set baseline > + # b. it's not minimum instruction set, but compiler support > + if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and cc.check_header('arm_sve.h') > + cflags += ['-DCC_SVE_SUPPORT'] > sources += files('hns3_rxtx_vec_sve.c') > + elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') > + sve_cflags = ['-DCC_SVE_SUPPORT'] > + foreach flag: cflags > + # filterout -march -mcpu -mtune > + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) > + sve_cflags += flag > + endif > + endforeach > + hns3_sve_lib = static_library('hns3_sve_lib', > + 'hns3_rxtx_vec_sve.c', > + dependencies: [static_rte_ethdev], > + include_directories: includes, > + c_args: [sve_cflags, '-march=armv8.2-a+sve']) > + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') > endif > endif >