Re: [dpdk-dev] [PATCH v5 0/3] support both PIO and MMIO BAR for virtio PMD

["谢华伟(此时此刻）" <huawei.xhw@alibaba-inc.com>]

Hi Ferruh:

Comments to this v5 version?

On 2020/10/22 23:51, 谢华伟(此时此刻） wrote:
> From: "huawei.xhw" <huawei.xhw@alibaba-inc.com>
>
> Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
> virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
>
> Kernel supports both PIO  and MMIO BAR for legacy virtio-pci device. We handles
> different type of BAR in the similar way.
>
> In previous implementation, with igb_uio we get PIO address from igb_uio
> sysfs entry; with uio_pci_generic, we get PIO address from
> /proc/ioports.
> For PIO/MMIO RW, there is different path for different drivers and arch.
> For VFIO, PIO/MMIO RW is through syscall, which has big performance
> issue.
> On X86, it assumes only PIO is supported.
>
> All of the above is too much twisted.
> This patch unifies the way to get both PIO and MMIO address for different driver
> and arch, all from standard resource attr under pci sysfs.
>
> We distinguish PIO and MMIO by their address like how kernel does. It is ugly but works.
>
> v2 changes:
> 	 - add more explanation in the commit message
>
> v3 changes:
> 	 - fix patch format issues
>
> v4 changes:
> 	 - fixes for RTE_KDRV_UIO_GENERIC -> RTE_PCI_KDRV_UIO_GENERIC
>
> v5 changes:
> 	 - split into three seperate patches
>
> huawei.xhw (3):
>    PCI: use PCI standard sysfs entry to get PIO address
>    PCI: support MMIO in rte_pci_ioport_map/unap/read/write
>    PCI: don't use vfio ioctl call to access PIO resource
>
>   drivers/bus/pci/linux/pci.c     |  89 +-------------------
>   drivers/bus/pci/linux/pci_uio.c | 177 ++++++++++++++++++++++++++++------------
>   2 files changed, 128 insertions(+), 138 deletions(-)
>