From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53093A053D; Fri, 17 Jul 2020 17:59:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F17C42C2B; Fri, 17 Jul 2020 17:59:58 +0200 (CEST) Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id E5D052C01 for ; Fri, 17 Jul 2020 17:59:57 +0200 (CEST) Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 922495C012A; Fri, 17 Jul 2020 11:59:57 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute7.internal (MEProxy); Fri, 17 Jul 2020 11:59:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm1; bh= T1KzFLVTZmu9wwRzZEsQ6LIJmhV1hnxo1nJ1YaZ7MfM=; b=uMAiCMAErBDfabAu xxZqo3IwGsjx4e3uPPznUSVf4UCr2BUsNyVIbV06eCucYRf5zNYuSrP++Xt5W9Ek nogJusXDTNxNJn0AV6w8s0TeVP2yhVMRY2ee12ZG4YYy0o9xQagrlQBx74LNAbXJ O5FQydREy3/3fuD8lAqBXFPuIGBFfsnlB4DoUSL/ouqmqnG3dFt6B4BhIafYhsmY GUwoEIEsHXVgik7tpnikUmyIJI0TzALEgYjsy6ZInnMEbJbR/2pbK7OLoXX8sTIk NI4TWik4fi/m6FVcGL1Wh9q6Y67lMV+4n6CTiG99pCW3AidzL4g4rzsq/Q8Eh86r cB2K6A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=T1KzFLVTZmu9wwRzZEsQ6LIJmhV1hnxo1nJ1YaZ7M fM=; b=uYWMi4+XUsAfLhNtzC2pP36TeWVaLrNNu60jINQ+zXkAVRITwonpnkBpJ EjmcCbTjsryv2vQ9dXhMrHmoz8Qf+9j1FLRhj9GztOKR61slUC7LheUlr8qZKevu zxByKUUVkh4wl9LGiZFZk7ZBrJzlTvMZMqQNpk96f/lu5Fb722KWb0MTp9/Fxy4T 88pI+7kK5exnOSmf/nogrFkiia7y9ysd5GzHZvdplzXDulznybq8u2Y70fo+qnSr PgefxhEz/bA1CI/D8xpR58u6qVmSUt0R4ep4eYbGp27/odV436CrZCUsUdQlYguY 3q81+u2+fzpZvTQfga8OJ9Xm4vd/w== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduiedrfeejgddthecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthhqredttddtjeenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpeekteehtdeivefhieegjeelgedufeejheekkeetueevieeuvdevuedt jeevheevteenucfkphepjeejrddufeegrddvtdefrddukeegnecuvehluhhsthgvrhfuih iivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepthhhohhmrghssehmohhnjhgrlhho nhdrnhgvth X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 8AEA0306005F; Fri, 17 Jul 2020 11:59:56 -0400 (EDT) From: Thomas Monjalon To: Slava Ovsiienko Cc: "dev@dpdk.org" , Matan Azrad , Raslan Darawsheh Date: Fri, 17 Jul 2020 17:59:55 +0200 Message-ID: <7707630.AmxAOCipGc@thomas> In-Reply-To: References: <1591771085-24959-1-git-send-email-viacheslavo@mellanox.com> <24924170.TV8gEDprjA@thomas> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 3/3] common/mlx5: fix DevX register access opcode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 17/07/2020 17:23, Slava Ovsiienko: >=20 > > -----Original Message----- > > From: Thomas Monjalon > > Sent: Friday, July 17, 2020 18:19 > > To: Slava Ovsiienko > > Cc: dev@dpdk.org; Matan Azrad ; Raslan > > Darawsheh > > Subject: Re: [PATCH 3/3] common/mlx5: fix DevX register access opcode > >=20 > > 17/07/2020 17:11, Slava Ovsiienko: > > > From: Thomas Monjalon > > > > 17/07/2020 16:28, Viacheslav Ovsiienko: > > > > > The dedicated MLX5_CMD_OP_ACCESS_REGISTER_USER opcode must > > be > > > > used to > > > > > read hardware register content from unprotected mode. > > > > > > > > Otherwise? What was broken? > > > > > > Otherwise the MLX5_CMD_OP_ACCESS_REGISTER was used, it returned > > > EINVAL and register value was not read. It was supposed to enable > > > ACCESS_REGISTER operation from user mode in kernel driver to read > > > registers, but eventually it was replaced with ACCESS_REGISTER_USER > > dedicated operation. > > > > > > mlx5 PMD does not rely on this feature strongly, if register reading > > > fails it deduces the timestamp mode from reported timestamp counter > > > frequency. > >=20 > > OK I think some of these explanations deserve to be in the commit log. >=20 > M-m-m-m, this is quite tiny 2-lines fix, we are going to squash it befor= e rc2 =F0=9F=98=8A > OK, will add the comment about dedicated opcode. If the patch is squashed with the root cause, no need to explain indeed.