From: fengchengwen <fengchengwen@huawei.com>
To: Rahul Bhansali <rbhansali@marvell.com>,
Ruifeng Wang <Ruifeng.Wang@arm.com>,
"dev@dpdk.org" <dev@dpdk.org>,
Jan Viktorin <viktorin@rehivetech.com>,
Bruce Richardson <bruce.richardson@intel.com>
Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>, nd <nd@arm.com>
Subject: Re: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k
Date: Sat, 7 May 2022 08:52:42 +0800 [thread overview]
Message-ID: <78cbcbf9-1495-cc2d-d11d-04ed4b21e206@huawei.com> (raw)
In-Reply-To: <CO6PR18MB3844462C5C56DF207A0C86B0B8C59@CO6PR18MB3844.namprd18.prod.outlook.com>
On 2022/5/6 21:17, Rahul Bhansali wrote:
>
>
>> -----Original Message-----
>> From: Ruifeng Wang <Ruifeng.Wang@arm.com>
>> Sent: Friday, May 6, 2022 12:53 PM
>> To: fengchengwen <fengchengwen@huawei.com>; Rahul Bhansali
>> <rbhansali@marvell.com>; dev@dpdk.org; Jan Viktorin
>> <viktorin@rehivetech.com>; Bruce Richardson <bruce.richardson@intel.com>
>> Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; nd <nd@arm.com>
>> Subject: RE: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k
>>
>>> -----Original Message-----
>>> From: fengchengwen <fengchengwen@huawei.com>
>>> Sent: Friday, May 6, 2022 2:36 PM
>>> To: Rahul Bhansali <rbhansali@marvell.com>; dev@dpdk.org; Ruifeng Wang
>>> <Ruifeng.Wang@arm.com>; Jan Viktorin <viktorin@rehivetech.com>; Bruce
>>> Richardson <bruce.richardson@intel.com>
>>> Cc: jerinj@marvell.com
>>> Subject: Re: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k
>>>
>>> On 2022/5/6 12:54, Rahul Bhansali wrote:
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: fengchengwen <fengchengwen@huawei.com>
>>>>> Sent: Friday, May 6, 2022 8:00 AM
>>>>> To: Rahul Bhansali <rbhansali@marvell.com>; dev@dpdk.org; Ruifeng
>>>>> Wang <ruifeng.wang@arm.com>; Jan Viktorin
>>> <viktorin@rehivetech.com>;
>>>>> Bruce Richardson <bruce.richardson@intel.com>
>>>>> Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>>>>> Subject: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k
>>>>>
>>>>> External Email
>>>>>
>>>>> -------------------------------------------------------------------
>>>>> --
>>>>> - On 2022/5/5 22:27, Rahul Bhansali wrote:
>>>>>> This disable the SVE flag for cn10k.
>>>>>>
>>>>>> Performance impact:-
>>>>>> With l3fwd example, lpm lookup performance increased by ~21% if
>>> Neon
>>>>>> is used instead of SVE.
>>>>>>
>>>>>> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
>>>>>> ---
>>>>>> config/arm/meson.build | 3 ++-
>>>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>>>>> dafb342cc6..39b7a1270c 100644
>>>>>> --- a/config/arm/meson.build
>>>>>> +++ b/config/arm/meson.build
>>>>>> @@ -281,7 +281,8 @@ soc_cn10k = {
>>>>>> ],
>>>>>> 'part_number': '0xd49',
>>>>>> 'extra_march_features': ['crypto'],
>>>>>> - 'numa': false
>>>>>> + 'numa': false,
>>>>>> + 'sve': false
>>>>>
>>>>> Suggest remove sve2 flag:
>>>>> '0xd49': {
>>>>> 'march': 'armv8.5-a',
>>>>> 'march_features': ['sve2'], ---remove 'sve2'
>>>>> 'flags': [
>>>>> ['RTE_MACHINE', '"neoverse-n2"'],
>>>>> ['RTE_ARM_FEATURE_ATOMICS', true],
>>>>> ['RTE_MAX_LCORE', 64],
>>>>> ['RTE_MAX_NUMA_NODES', 1]
>>>>> ]
>>>>> }
>>>>>
>>>> If I remove here, then this will also change for " Arm Neoverse N2
>>>> soc_n2",
>>> because part_number is same, Right ?
>>>> Because of this reason, I thought to have separate flag instead of
>>>> updating
>>> march_features.
>>>
>>> This new add flag only impact hand-writen sve code, but
>>> auto-vectorization is also enabled when sve is enabled at march_features.
>> Agree.
>>
>>> Maybe NEON-based automated vector code performs better than SVE-
>>> based.
>>>
>>> I think it's OK to add separate flag in soc_xxx struct, but suggest it
>>> also impact auto-vectorization.
>> I would suggest the flag to control only RTE_HAS_SVE_ACLE, i.e. hand written
>> code using SVE C language intrinsics.
>> For auto-vectorization, I think it is compilers duty to vectorize in the most
>> performant way, use whatever resource hardware provided.
>>
>
> I agree to the point of auto-vectorization to let it be if supported and control the RTE_HAS_SVE_ACLE for hand-written SVE C code.
Agree with the point: the flag to control only RTE_HAS_SVE_ACLE
Maybe sve_acle is more appropriate for the new flag.
>
>>>
>>> So for one soc which test or optimize well on sve, it could turn the flag to true.
>>>
>>>>
>>>>>> }
>>>>>>
>>>>>> soc_dpaa = {
>>>>>>
>>>>
>
next prev parent reply other threads:[~2022-05-07 0:52 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 14:27 [PATCH 1/2] config/arm: add SVE control flag Rahul Bhansali
2022-05-05 14:27 ` [PATCH 2/2] config/arm: disable SVE for cn10k Rahul Bhansali
2022-05-06 2:29 ` fengchengwen
2022-05-06 4:54 ` [EXT] " Rahul Bhansali
2022-05-06 6:36 ` fengchengwen
2022-05-06 7:23 ` Ruifeng Wang
2022-05-06 13:17 ` Rahul Bhansali
2022-05-07 0:52 ` fengchengwen [this message]
2022-05-05 14:39 ` [PATCH 1/2] config/arm: add SVE control flag Bruce Richardson
2022-05-06 14:16 ` [EXT] " Rahul Bhansali
2022-05-06 2:23 ` fengchengwen
2022-05-07 9:39 ` [PATCH v2 1/2] config/arm: add SVE ACLE " Rahul Bhansali
2022-05-07 9:39 ` [PATCH v2 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-09 0:49 ` [PATCH v2 1/2] config/arm: add SVE ACLE control flag fengchengwen
2022-05-09 9:46 ` [PATCH v3 " Rahul Bhansali
2022-05-09 9:46 ` [PATCH v3 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-09 10:19 ` [PATCH v4 1/2] config/arm: add SVE ACLE control flag Rahul Bhansali
2022-05-09 10:19 ` [PATCH v4 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-10 2:57 ` fengchengwen
2022-05-11 1:35 ` Ruifeng Wang
2022-05-11 4:12 ` Honnappa Nagarahalli
2022-05-10 2:57 ` [PATCH v4 1/2] config/arm: add SVE ACLE control flag fengchengwen
2022-05-11 1:35 ` Ruifeng Wang
2022-05-11 4:09 ` Honnappa Nagarahalli
2022-05-17 7:56 ` Juraj Linkeš
2022-05-18 9:18 ` Rahul Bhansali
2022-05-18 14:45 ` Juraj Linkeš
2022-05-19 13:28 ` [PATCH v5 " Rahul Bhansali
2022-05-19 13:28 ` [PATCH v5 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-06-01 22:38 ` Thomas Monjalon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=78cbcbf9-1495-cc2d-d11d-04ed4b21e206@huawei.com \
--to=fengchengwen@huawei.com \
--cc=Ruifeng.Wang@arm.com \
--cc=bruce.richardson@intel.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=nd@arm.com \
--cc=rbhansali@marvell.com \
--cc=viktorin@rehivetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).