From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from tyo202.gate.nec.co.jp (TYO202.gate.nec.co.jp [210.143.35.52]) by dpdk.org (Postfix) with ESMTP id 815E01F5 for ; Thu, 25 Sep 2014 02:29:59 +0200 (CEST) Received: from mailgate3.nec.co.jp ([10.7.69.197]) by tyo202.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id s8P0aA9E005985; Thu, 25 Sep 2014 09:36:10 +0900 (JST) Received: from mailsv4.nec.co.jp (imss61.nec.co.jp [10.7.69.156]) by mailgate3.nec.co.jp (8.11.7/3.7W-MAILGATE-NEC) with ESMTP id s8P0aAR11550; Thu, 25 Sep 2014 09:36:10 +0900 (JST) Received: from mail01b.kamome.nec.co.jp (mail01b.kamome.nec.co.jp [10.25.43.2]) by mailsv4.nec.co.jp (8.13.8/8.13.4) with ESMTP id s8P0ZrrU021977; Thu, 25 Sep 2014 09:36:10 +0900 (JST) Received: from bpxc99gp.gisp.nec.co.jp ([10.38.151.145] [10.38.151.145]) by mail01b.kamome.nec.co.jp with ESMTP id BT-MMP-2085628; Thu, 25 Sep 2014 09:35:52 +0900 Received: from BPXM14GP.gisp.nec.co.jp ([169.254.1.136]) by BPXC17GP.gisp.nec.co.jp ([10.38.151.145]) with mapi id 14.03.0174.002; Thu, 25 Sep 2014 09:35:51 +0900 From: Hiroshi Shimamoto To: Thomas Monjalon , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier Thread-Index: AQHP2ArG85sYq/F0GkOG2kfCJWfWLpwQ+Zlg Date: Thu, 25 Sep 2014 00:35:51 +0000 Message-ID: <7F861DC0615E0C47A872E6F3C5FCDDBD02AD9F40@BPXM14GP.gisp.nec.co.jp> References: <7F861DC0615E0C47A872E6F3C5FCDDBD011A9934@BPXM14GP.gisp.nec.co.jp> <1855491.X6obi8qxOV@xps13> In-Reply-To: <1855491.X6obi8qxOV@xps13> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.205.5.123] Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: Hayato Momma Subject: Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Sep 2014 00:30:00 -0000 > Subject: Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier >=20 > 2014-09-11 07:48, Hiroshi Shimamoto: > > x86 can keep store ordering with standard operations. >=20 > Are we sure it's always the case (including old 32-bit CPU)? > I would prefer to have a reference here. I know we already discussed > this kind of things but having a reference in commit log could help > for future discussions. >=20 > > Using memory barrier is much expensive in main packet processing loop. > > Removing this improves xmit/recv packet performance. > > > > We can see performance improvements with memnic-tester. > > Using Xeon E5-2697 v2 @ 2.70GHz, 4 vCPU. > > size | before | after > > 64 | 4.18Mpps | 4.59Mpps > > 128 | 3.85Mpps | 4.87Mpps > > 256 | 4.01Mpps | 4.72Mpps > > 512 | 3.52Mpps | 4.41Mpps > > 1024 | 3.18Mpps | 3.64Mpps > > 1280 | 2.86Mpps | 3.15Mpps > > 1518 | 2.59Mpps | 2.87Mpps > > > > Note: we have to take care if we use temporal cache. >=20 > Please, could you explain this last sentence? Oops, I have mistaken the word, "temporal" should be "non-temporal". By the way, there are some instructions which use non-temporal cache liek MOVNTx series. The store ordering of these instructions is not kept. Ref. Intel Software Developer Manual Vol.1 10.4.6.2 Caching of Temporal vs. Non-Temporal Data Vol.3 8.2 Memory Ordering thanks, Hiroshi >=20 > Thanks > -- > Thomas