* [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro
@ 2018-04-17 20:04 Pavan Nikhilesh
2018-04-18 17:17 ` Ferruh Yigit
0 siblings, 1 reply; 4+ messages in thread
From: Pavan Nikhilesh @ 2018-04-17 20:04 UTC (permalink / raw)
To: ravi1.kumar, ferruh.yigit, thomas; +Cc: dev, Pavan Nikhilesh
Due to missing ____cacheline_aligned definition compiler treats it as a
global variable replace it with proper cache alignment macro.
Fixes: 9e890103267e ("net/axgbe: add Rx/Tx setup")
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
---
drivers/net/axgbe/axgbe_rxtx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx.h
index 1ec6c2ca6..917da58ce 100644
--- a/drivers/net/axgbe/axgbe_rxtx.h
+++ b/drivers/net/axgbe/axgbe_rxtx.h
@@ -94,7 +94,7 @@ struct axgbe_rx_queue {
/* Number of mbufs allocated from pool*/
uint64_t mbuf_alloc;
-} ____cacheline_aligned;
+} __rte_cache_aligned;
/*Tx descriptor format */
struct axgbe_tx_desc {
--
2.17.0
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro
2018-04-17 20:04 [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro Pavan Nikhilesh
@ 2018-04-18 17:17 ` Ferruh Yigit
2018-04-18 17:44 ` Ferruh Yigit
0 siblings, 1 reply; 4+ messages in thread
From: Ferruh Yigit @ 2018-04-18 17:17 UTC (permalink / raw)
To: Pavan Nikhilesh, ravi1.kumar, thomas; +Cc: dev
On 4/17/2018 9:04 PM, Pavan Nikhilesh wrote:
> Due to missing ____cacheline_aligned definition compiler treats it as a
> global variable replace it with proper cache alignment macro.
>
> Fixes: 9e890103267e ("net/axgbe: add Rx/Tx setup")
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro
2018-04-18 17:17 ` Ferruh Yigit
@ 2018-04-18 17:44 ` Ferruh Yigit
2018-04-23 6:32 ` Kumar, Ravi1
0 siblings, 1 reply; 4+ messages in thread
From: Ferruh Yigit @ 2018-04-18 17:44 UTC (permalink / raw)
To: Pavan Nikhilesh, ravi1.kumar, thomas; +Cc: dev
On 4/18/2018 6:17 PM, Ferruh Yigit wrote:
> On 4/17/2018 9:04 PM, Pavan Nikhilesh wrote:
>> Due to missing ____cacheline_aligned definition compiler treats it as a
>> global variable replace it with proper cache alignment macro.
>>
>> Fixes: 9e890103267e ("net/axgbe: add Rx/Tx setup")
>>
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
>
> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Applied to dpdk-next-net/master, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro
2018-04-18 17:44 ` Ferruh Yigit
@ 2018-04-23 6:32 ` Kumar, Ravi1
0 siblings, 0 replies; 4+ messages in thread
From: Kumar, Ravi1 @ 2018-04-23 6:32 UTC (permalink / raw)
To: Ferruh Yigit, Pavan Nikhilesh, thomas; +Cc: dev
>On 4/18/2018 6:17 PM, Ferruh Yigit wrote:
>> On 4/17/2018 9:04 PM, Pavan Nikhilesh wrote:
>>> Due to missing ____cacheline_aligned definition compiler treats it as
>>> a global variable replace it with proper cache alignment macro.
>>>
>>> Fixes: 9e890103267e ("net/axgbe: add Rx/Tx setup")
>>>
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
>>
>> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
>
>Applied to dpdk-next-net/master, thanks.
>
Thanks a lot Ferruh.
Regards,
Ravi
^ permalink raw reply [flat|nested] 4+ messages in thread
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2018-04-17 20:04 [dpdk-dev] [PATCH] net/axgbe: fix incorrect cache alignment macro Pavan Nikhilesh
2018-04-18 17:17 ` Ferruh Yigit
2018-04-18 17:44 ` Ferruh Yigit
2018-04-23 6:32 ` Kumar, Ravi1
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