From: Kevin Traynor <ktraynor@redhat.com>
To: pbhagavatula@marvell.com, jerinj@marvell.com,
Jan Viktorin <viktorin@rehivetech.com>,
Ruifeng Wang <ruifeng.wang@arm.com>,
Bruce Richardson <bruce.richardson@intel.com>
Cc: dev@dpdk.org
Subject: Re: [PATCH] config/cn10k: align mempool elements to 128 bytes
Date: Tue, 14 Dec 2021 10:30:00 +0000 [thread overview]
Message-ID: <7be191c7-298b-ebdf-2aeb-1080ff1eaae8@redhat.com> (raw)
In-Reply-To: <20211213110615.4458-1-pbhagavatula@marvell.com>
On 13/12/2021 11:06, pbhagavatula@marvell.com wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> Mempool elements are by default aligned to CACHELINE_SIZE.
> In CN10K cacheline size is 64B but the RoC requires buffers to be
> aligned to 128B.
It would be good to say what the implication is in the commit message.
> Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> 128 bytes.
>
Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
This is for backport? If so please add stable@ tag
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> config/arm/meson.build | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 213324d262..33afe1a9ad 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -276,7 +276,8 @@ soc_cn10k = {
> 'implementer' : '0x41',
> 'flags': [
> ['RTE_MAX_LCORE', 24],
> - ['RTE_MAX_NUMA_NODES', 1]
> + ['RTE_MAX_NUMA_NODES', 1],
> + ['RTE_MEMPOOL_ALIGN', 128]
> ],
> 'part_number': '0xd49',
> 'extra_march_features': ['crypto'],
>
prev parent reply other threads:[~2021-12-14 10:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-13 11:06 pbhagavatula
2021-12-14 9:23 ` Ruifeng Wang
2022-01-20 9:51 ` Jerin Jacob
2022-01-21 9:37 ` Jerin Jacob
2022-02-12 14:14 ` Thomas Monjalon
2021-12-14 10:30 ` Kevin Traynor [this message]
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