From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83048454EF; Tue, 25 Jun 2024 13:27:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7B68D43359; Tue, 25 Jun 2024 13:19:03 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id B4C1542D2B for ; Tue, 25 Jun 2024 13:17:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314264; x=1750850264; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5jj9DTlMEpbuT2Xs2kNa50f0F7GahZo1yggP5jzxnGU=; b=jOREXLZa38RoGiaN/TkH9mWXagk3rW9yBdxUVyXWcr36xatj+6BkeH+S JpzcfwyNgKVvnUhAvTlsJMtGx6BG8OFIOrh2AgD6KRoEZJkrokFAdkE+0 q5C5JPaK34oCYtflLHg7/syghqfvcvWFbsRlBVTzfuX2Jim2wfilDF6nL M/Na6fRloDjIY6QUVcfJqUZi0CYDvi9wf8NOmcGcoUC42Kie9ULWxcpyl lbl+fj1mSd4zBEhSfzI0AhROSrmgftIvubn8mylE4Xy3Hes8EmDOEDRFT T1jNm7cwDkisgYqzOldZ9c84lJTJ+jVY6/od7Mn1/E1TjDjha04ULgWLW g==; X-CSE-ConnectionGUID: sk1dnyohRomZ4FHiWqfiTg== X-CSE-MsgGUID: nQ+pKxR6Swu7oO2lSF01mg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080561" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080561" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:17:43 -0700 X-CSE-ConnectionGUID: XOowvXFwRZ6yoFDc1uD2YA== X-CSE-MsgGUID: spjIrVGmSaeGoVgj5pHB5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719660" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:17:43 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Sergey Temerkhanov , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 101/129] net/ice/base: allow skipping main timer programming Date: Tue, 25 Jun 2024 12:13:46 +0100 Message-ID: <7d8988ddc5bcd6b28cb29191e12eccdcb132f626.1719313663.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sergey Temerkhanov Allow initialization functions to skip main timer programming. Signed-off-by: Sergey Temerkhanov Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 31 ++++++++++++++++++++----------- drivers/net/ice/base/ice_ptp_hw.h | 9 ++++++--- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 8cc1478dcc..250a74826b 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5802,6 +5802,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, * ice_ptp_init_time - Initialize device time to provided value * @hw: pointer to HW struct * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) + * @wr_main_tmr: program the main timer * * Initialize the device to the specified time provided. This requires a three * step process: @@ -5811,7 +5812,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, * 3) issue an init_time timer command to synchronously switch both the source * and port timers to the new init time value at the next clock cycle. */ -int ice_ptp_init_time(struct ice_hw *hw, u64 time) +int ice_ptp_init_time(struct ice_hw *hw, u64 time, bool wr_main_tmr) { int err; u8 tmr_idx; @@ -5823,9 +5824,11 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) if (hw->phy_model == ICE_PHY_E830) return ice_ptp_write_direct_phc_time_e830(hw, time); - wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + if (wr_main_tmr) { + wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + } /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ @@ -5853,8 +5856,9 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) * ice_ptp_write_incval - Program PHC with new increment value * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * - * Program the PHC with a new increment value. This requires a three-step + * Program the timers with a new increment value. This requires a three-step * process: * * 1) Write the increment value to the source timer shadow registers @@ -5863,7 +5867,8 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) * the source and port timers to the new increment value at the next clock * cycle. */ -int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) +int ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { int err; u8 tmr_idx; @@ -5874,9 +5879,11 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) if (hw->phy_model == ICE_PHY_E830) return ice_ptp_write_direct_incval_e830(hw, incval); - /* Shadow Adjust */ - wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); - wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + if (wr_main_tmr) { + /* Shadow Adjust */ + wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); + wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + } switch (hw->phy_model) { case ICE_PHY_ETH56G: @@ -5902,17 +5909,19 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) * ice_ptp_write_incval_locked - Program new incval while holding semaphore * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * * Program a new PHC incval while holding the PTP semaphore. */ -int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) +int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { int err; if (!ice_ptp_lock(hw)) return ICE_ERR_NOT_READY; - err = ice_ptp_write_incval(hw, incval); + err = ice_ptp_write_incval(hw, incval, wr_main_tmr); ice_ptp_unlock(hw); diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index d4bee8ce40..bd6bb3e839 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -142,9 +142,12 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd); -int ice_ptp_init_time(struct ice_hw *hw, u64 time); -int ice_ptp_write_incval(struct ice_hw *hw, u64 incval); -int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); +int ice_ptp_init_time(struct ice_hw *hw, u64 time, + bool wr_main_tmr); +int ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); +int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); int ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 9447b44141..64ac64326a 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -6460,7 +6460,7 @@ ice_timesync_enable(struct rte_eth_dev *dev) return -1; } - ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810); + ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, true); if (ret) { PMD_DRV_LOG(ERR, "Failed to write PHC increment time value"); -- 2.43.0