From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6CF4A034C; Tue, 18 Aug 2020 20:48:24 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3EEE82BE3; Tue, 18 Aug 2020 20:48:24 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 6257E2B94 for ; Tue, 18 Aug 2020 20:48:22 +0200 (CEST) IronPort-SDR: jPAZdX9mxDKmZGw1AnO+Sizc3h4nEsp3zHw7xTIH9q71e4+tpv4fRQe0DInkOd0lzYss7ys3Vz VliaAydqolgg== X-IronPort-AV: E=McAfee;i="6000,8403,9717"; a="239819274" X-IronPort-AV: E=Sophos;i="5.76,328,1592895600"; d="scan'208";a="239819274" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 11:48:21 -0700 IronPort-SDR: h/SSZpSbYnxovr5eaZoZg5KRUFSfpC87ytVesYZ7s4oh7mILsWX6GNvAU0PB08U81ETHkJp3Po IOvqdYo+7aGA== X-IronPort-AV: E=Sophos;i="5.76,328,1592895600"; d="scan'208";a="471917495" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.213.234.30]) ([10.213.234.30]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 11:48:19 -0700 To: Bruce Richardson Cc: Ruifeng Wang , hemant.agrawal@nxp.com, jerinj@marvell.com, viktorin@rehivetech.com, dev@dpdk.org, honnappa.nagarahalli@arm.com, phil.yang@arm.com, nd@arm.com References: <20200814060320.86238-1-ruifeng.wang@arm.com> <20200818145310.GI500@bricha3-MOBL.ger.corp.intel.com> From: Ferruh Yigit Autocrypt: addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; keydata= mQINBFXZCFABEADCujshBOAaqPZpwShdkzkyGpJ15lmxiSr3jVMqOtQS/sB3FYLT0/d3+bvy qbL9YnlbPyRvZfnP3pXiKwkRoR1RJwEo2BOf6hxdzTmLRtGtwWzI9MwrUPj6n/ldiD58VAGQ +iR1I/z9UBUN/ZMksElA2D7Jgg7vZ78iKwNnd+vLBD6I61kVrZ45Vjo3r+pPOByUBXOUlxp9 GWEKKIrJ4eogqkVNSixN16VYK7xR+5OUkBYUO+sE6etSxCr7BahMPKxH+XPlZZjKrxciaWQb +dElz3Ab4Opl+ZT/bK2huX+W+NJBEBVzjTkhjSTjcyRdxvS1gwWRuXqAml/sh+KQjPV1PPHF YK5LcqLkle+OKTCa82OvUb7cr+ALxATIZXQkgmn+zFT8UzSS3aiBBohg3BtbTIWy51jNlYdy ezUZ4UxKSsFuUTPt+JjHQBvF7WKbmNGS3fCid5Iag4tWOfZoqiCNzxApkVugltxoc6rG2TyX CmI2rP0mQ0GOsGXA3+3c1MCdQFzdIn/5tLBZyKy4F54UFo35eOX8/g7OaE+xrgY/4bZjpxC1 1pd66AAtKb3aNXpHvIfkVV6NYloo52H+FUE5ZDPNCGD0/btFGPWmWRmkPybzColTy7fmPaGz cBcEEqHK4T0aY4UJmE7Ylvg255Kz7s6wGZe6IR3N0cKNv++O7QARAQABtCVGZXJydWggWWln aXQgPGZlcnJ1aC55aWdpdEBpbnRlbC5jb20+iQJsBBMBCgBWAhsDAh4BAheABQsJCAcDBRUK CQgLBRYCAwEABQkKqZZ8FiEE0jZTh0IuwoTjmYHH+TPrQ98TYR8FAl6ha3sXGHZrczovL2tl eXMub3BlbnBncC5vcmcACgkQ+TPrQ98TYR8uLA//QwltuFliUWe60xwmu9sY38c1DXvX67wk UryQ1WijVdIoj4H8cf/s2KtyIBjc89R254KMEfJDao/LrXqJ69KyGKXFhFPlF3VmFLsN4XiT PSfxkx8s6kHVaB3O183p4xAqnnl/ql8nJ5ph9HuwdL8CyO5/7dC/MjZ/mc4NGq5O9zk3YRGO lvdZAp5HW9VKW4iynvy7rl3tKyEqaAE62MbGyfJDH3C/nV/4+mPc8Av5rRH2hV+DBQourwuC ci6noiDP6GCNQqTh1FHYvXaN4GPMHD9DX6LtT8Fc5mL/V9i9kEVikPohlI0WJqhE+vQHFzR2 1q5nznE+pweYsBi3LXIMYpmha9oJh03dJOdKAEhkfBr6n8BWkWQMMiwfdzg20JX0o7a/iF8H 4dshBs+dXdIKzPfJhMjHxLDFNPNH8zRQkB02JceY9ESEah3wAbzTwz+e/9qQ5OyDTQjKkVOo cxC2U7CqeNt0JZi0tmuzIWrfxjAUulVhBmnceqyMOzGpSCQIkvalb6+eXsC9V1DZ4zsHZ2Mx Hi+7pCksdraXUhKdg5bOVCt8XFmx1MX4AoV3GWy6mZ4eMMvJN2hjXcrreQgG25BdCdcxKgqp e9cMbCtF+RZax8U6LkAWueJJ1QXrav1Jk5SnG8/5xANQoBQKGz+yFiWcgEs9Tpxth15o2v59 gXK5Ag0EV9ZMvgEQAKc0Db17xNqtSwEvmfp4tkddwW9XA0tWWKtY4KUdd/jijYqc3fDD54ES YpV8QWj0xK4YM0dLxnDU2IYxjEshSB1TqAatVWz9WtBYvzalsyTqMKP3w34FciuL7orXP4Ai bPtrHuIXWQOBECcVZTTOdZYGAzaYzxiAONzF9eTiwIqe9/oaOjTwTLnOarHt16QApTYQSnxD UQljeNvKYt1lZE/gAUUxNLWsYyTT+22/vU0GDUahsJxs1+f1yEr+OGrFiEAmqrzpF0lCS3f/ 3HVTU6rS9cK3glVUeaTF4+1SK5ZNO35piVQCwphmxa+dwTG/DvvHYCtgOZorTJ+OHfvCnSVj sM4kcXGjJPy3JZmUtyL9UxEbYlrffGPQI3gLXIGD5AN5XdAXFCjjaID/KR1c9RHd7Oaw0Pdc q9UtMLgM1vdX8RlDuMGPrj5sQrRVbgYHfVU/TQCk1C9KhzOwg4Ap2T3tE1umY/DqrXQgsgH7 1PXFucVjOyHMYXXugLT8YQ0gcBPHy9mZqw5mgOI5lCl6d4uCcUT0l/OEtPG/rA1lxz8ctdFB VOQOxCvwRG2QCgcJ/UTn5vlivul+cThi6ERPvjqjblLncQtRg8izj2qgmwQkvfj+h7Ex88bI 8iWtu5+I3K3LmNz/UxHBSWEmUnkg4fJlRr7oItHsZ0ia6wWQ8lQnABEBAAGJAjwEGAEKACYC GwwWIQTSNlOHQi7ChOOZgcf5M+tD3xNhHwUCXqFrngUJCKxSYAAKCRD5M+tD3xNhH3YWD/9b cUiWaHJasX+OpiuZ1Li5GG3m9aw4lR/k2lET0UPRer2Jy1JsL+uqzdkxGvPqzFTBXgx/6Byz EMa2mt6R9BCyR286s3lxVS5Bgr5JGB3EkpPcoJT3A7QOYMV95jBiiJTy78Qdzi5LrIu4tW6H o0MWUjpjdbR01cnj6EagKrDx9kAsqQTfvz4ff5JIFyKSKEHQMaz1YGHyCWhsTwqONhs0G7V2 0taQS1bGiaWND0dIBJ/u0pU998XZhmMzn765H+/MqXsyDXwoHv1rcaX/kcZIcN3sLUVcbdxA WHXOktGTQemQfEpCNuf2jeeJlp8sHmAQmV3dLS1R49h0q7hH4qOPEIvXjQebJGs5W7s2vxbA 5u5nLujmMkkfg1XHsds0u7Zdp2n200VC4GQf8vsUp6CSMgjedHeF9zKv1W4lYXpHp576ZV7T GgsEsvveAE1xvHnpV9d7ZehPuZfYlP4qgo2iutA1c0AXZLn5LPcDBgZ+KQZTzm05RU1gkx7n gL9CdTzVrYFy7Y5R+TrE9HFUnsaXaGsJwOB/emByGPQEKrupz8CZFi9pkqPuAPwjN6Wonokv ChAewHXPUadcJmCTj78Oeg9uXR6yjpxyFjx3vdijQIYgi5TEGpeTQBymLANOYxYWYOjXk+ae dYuOYKR9nbPv+2zK9pwwQ2NXbUBystaGyQ== Message-ID: <7db307d0-bdc7-6a5b-125f-0a4542f19056@intel.com> Date: Tue, 18 Aug 2020 19:48:17 +0100 MIME-Version: 1.0 In-Reply-To: <20200818145310.GI500@bricha3-MOBL.ger.corp.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [RFC PATCH] config: remap flags used for Arm platforms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 8/18/2020 3:53 PM, Bruce Richardson wrote: > On Tue, Aug 18, 2020 at 03:36:00PM +0100, Ferruh Yigit wrote: >> On 8/14/2020 7:03 AM, Ruifeng Wang wrote: >>> Flags are used to distinguish different platform architectures. >>> These flags can be used to pick different code paths for different >>> architectures at compile time. >>> For Arm platforms, there are 3 flags in use: RTE_ARCH_ARM, >>> RTE_ARCH_ARMv7 and RTE_ARCH_ARM64. >>> RTE_ARCH_ARM64 is used to flag 64-bit aarch64 platforms, >>> while RTE_ARCH_ARM & RTE_ARCH_ARMv7 are used to flag 32-bit platforms. >>> RTE_ARCH_ARMv7 is for ARMv7 platforms as its name suggested. >>> >>> The issue is that flag name RTE_ARCH_ARM is unclear and could cause >>> confusion. No info about platform word length is included in the name. >>> To make the flag names more clear, a naming scheme is proposed. >>> >>> RTE_ARCH_ARM >>> | >>> +----RTE_ARCH_ARM32 >>> | | >>> | +----RTE_ARCH_ARMv7 >>> | | >>> | +----RTE_ARCH_ARMv8_AARCH32 >>> | >>> +----RTE_ARCH_ARM64 >>> >>> RTE_ARCH_ARM32 will be used for 32-bit Arm platforms. >>> It includes RTE_ARCH_ARMv7 and RTE_ARCH_ARMv8_AARCH32. >>> RTE_ARCH_ARMv7 is for ARMv7 platforms. >>> RTE_ARCH_ARMv8_AARCH32 is for aarch32 state on aarch64 platforms. >>> RTE_ARCH_ARM64 is for 64-bit Arm platforms. >>> RTE_ARCH_ARM will be used for all Arm platforms, including RTE_ARCH_ARM32 >>> and RTE_ARCH_ARM64. >>> >>> To fit into the new naming scheme, current usage of RTE_ARCH_ARM in >>> project code is mapped to RTE_ARCH_ARM32. >>> >>> Suggested-by: Honnappa Nagarahalli >>> Signed-off-by: Ruifeng Wang >>> Reviewed-by: Phil Yang >>> --- >> >> <...> >> >>> @@ -6,7 +6,7 @@ >>> CONFIG_RTE_MACHINE="armv7a" >>> >>> CONFIG_RTE_ARCH="arm" >>> -CONFIG_RTE_ARCH_ARM=y >>> +CONFIG_RTE_ARCH_ARM32=y >>> CONFIG_RTE_ARCH_ARMv7=y >>> CONFIG_RTE_ARCH_ARM_TUNE="cortex-a9" >> >> According commit log message I thought 'RTE_ARCH_ARM' will be always set, isn't >> it the case? >> >> Is below wrong: >> aarch64 -> ARM | ARM64 | ARCH_64 >> armv7a -> ARM | ARM32 | ARMv7 >> aarch32 -> ARM | ARM32 | ARMv8_AARCH32 >> >> If so some of the 'defined(RTE_ARCH_ARM32) || defined(RTE_ARCH_ARM64)' checks >> can be simplified as 'defined(RTE_ARCH_ARM)' >> >> >> Also currently missing 'ARCH_64' flag implies the 32bit support, for all >> architectures, what about having a common 'ARCH_32' flag and use for all arch, >> instead of 'ARM32'? So something like below: >> aarch64 -> ARM | ARM64 | ARCH_64 >> armv7a -> ARM | ARMv7 | ARCH_32 >> aarch32 -> ARM | ARMv8_AARCH32 | ARCH_32 >> > Not sure why you would need ARCH_32, since it's basically just !ARCH_64. > Just to be more explicit, other than that same as '!ARCH_64'.