From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 349C51B209 for ; Mon, 2 Oct 2017 13:27:30 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Oct 2017 04:27:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,469,1500966000"; d="scan'208";a="905831591" Received: from smonroyx-mobl.ger.corp.intel.com (HELO [10.237.221.11]) ([10.237.221.11]) by FMSMGA003.fm.intel.com with ESMTP; 02 Oct 2017 04:27:28 -0700 To: Jerin Jacob References: <20171002100930.78602-1-sergio.gonzalez.monroy@intel.com> <20171002111738.79520-1-sergio.gonzalez.monroy@intel.com> <20171002112403.GA13389@jerin> Cc: dev@dpdk.org, harry.van.haaren@intel.com, bruce.richardson@intel.com From: Sergio Gonzalez Monroy Message-ID: <82b7e8fd-c614-fd1c-2bc6-5da8cce33ceb@intel.com> Date: Mon, 2 Oct 2017 12:27:28 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <20171002112403.GA13389@jerin> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v3] eal/x86: implement x86 specific tsc hz X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Oct 2017 11:27:31 -0000 On 02/10/2017 12:24, Jerin Jacob wrote: > -----Original Message----- >> Date: Mon, 2 Oct 2017 12:17:38 +0100 >> From: Sergio Gonzalez Monroy >> To: dev@dpdk.org >> CC: harry.van.haaren@intel.com, bruce.richardson@intel.com >> Subject: [dpdk-dev] [PATCH v3] eal/x86: implement x86 specific tsc hz >> X-Mailer: git-send-email 2.9.5 >> >> First, try to use CPUID Time Stamp Counter and Nominal Core Crystal >> Clock Information Leaf to determine the tsc hz on platforms that >> supports it (does not require privileged user). >> >> If the CPUID leaf is not available, then try to determine the tsc hz by >> reading the MSR 0xCE (requires privileged user). >> >> Default to the tsc hz estimation if both methods fail. >> >> Signed-off-by: Sergio Gonzalez Monroy >> Acked-by: Harry van Haaren >> Tested-by: Bruce Richardson >> --- >> DEPENDS on: >> http://dpdk.org/dev/patchwork/patch/29086/ >> >> v3: >> - acked-by and tested-by tags >> >> v2: >> - fix misspelled word in commit message >> - address comment for more clear code >> >> lib/librte_eal/common/arch/x86/rte_cycles.c | 142 +++++++++++++++++++++ >> .../common/include/arch/x86/rte_cycles.h | 7 +- >> lib/librte_eal/linuxapp/eal/Makefile | 1 + >> 3 files changed, 145 insertions(+), 5 deletions(-) >> create mode 100644 lib/librte_eal/common/arch/x86/rte_cycles.c >> + >> +static uint32_t >> +check_model_wsm_nhm(uint8_t model) >> +{ >> + switch (model) { >> + /* Westmere */ >> + case 0x25: >> + case 0x2C: >> + case 0x2F: >> + /* Nehalem */ >> + case 0x1E: >> + case 0x1F: >> + case 0x1A: > See next comment. > >> + case 0x2E: >> + return 1; >> + } >> + >> + return 0; >> +} >> + >> +static uint32_t >> +check_model_gdm_dnv(uint8_t model) >> +{ >> + switch (model) { >> + /* Goldmont */ >> + case 0x5C: >> + /* Denverton */ > Not adding "/* fall-through */" may break gcc 7 build. See Bruce's comment on: http://dpdk.org/ml/archives/dev/2017-September/074259.html Thanks, Sergio