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Fri, 13 Mar 2020 04:05:00 -0700 (PDT) To: dev@dpdk.org References: <1582778348-113547-15-git-send-email-nicolas.chautru@intel.com> <1583348102-13253-1-git-send-email-nicolas.chautru@intel.com> <1583348102-13253-14-git-send-email-nicolas.chautru@intel.com> From: Dave Burley Message-ID: <858de466-4943-b67f-b6d2-9be7ca9db6b3@accelercomm.com> Date: Fri, 13 Mar 2020 11:05:00 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1583348102-13253-14-git-send-email-nicolas.chautru@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Subject: Re: [dpdk-dev] [PATCH v3 13/14] test-bbdev: add support for FPGA driver initialization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Acked-by: Dave Burley On 04/03/2020 18:55, Nicolas Chautru wrote: > From: Nic Chautru > > Adding capacity to initialize the device driver from > the test-bbdev environment for the new device > FPGA for 5GNR FEC. > > Signed-off-by: Nic Chautru > --- > app/test-bbdev/Makefile | 3 +++ > app/test-bbdev/meson.build | 3 +++ > app/test-bbdev/test_bbdev_perf.c | 58 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 64 insertions(+) > > diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile > index c53982f..e951302 100644 > --- a/app/test-bbdev/Makefile > +++ b/app/test-bbdev/Makefile > @@ -24,5 +24,8 @@ LDLIBS += -lm > ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y) > LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec > endif > +ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y) > +LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec > +endif > > include $(RTE_SDK)/mk/rte.app.mk > diff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build > index 4f53a2e..e57e019 100644 > --- a/app/test-bbdev/meson.build > +++ b/app/test-bbdev/meson.build > @@ -10,3 +10,6 @@ deps += ['bbdev', 'bus_vdev'] > if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC') > deps += ['pmd_bbdev_fpga_lte_fec'] > endif > +if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC') > + deps += ['pmd_bbdev_fpga_5gnr_fec'] > +endif > \ No newline at end of file > diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c > index 1017b97..50ffee0 100644 > --- a/app/test-bbdev/test_bbdev_perf.c > +++ b/app/test-bbdev/test_bbdev_perf.c > @@ -39,6 +39,19 @@ > #define FLR_4G_TIMEOUT 610 > #endif > > +#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC > +#include > +#define FPGA_5GNR_PF_DRIVER_NAME ("intel_fpga_5gnr_fec_pf") > +#define FPGA_5GNR_VF_DRIVER_NAME ("intel_fpga_5gnr_fec_vf") > +#define VF_UL_5G_QUEUE_VALUE 4 > +#define VF_DL_5G_QUEUE_VALUE 4 > +#define UL_5G_BANDWIDTH 3 > +#define DL_5G_BANDWIDTH 3 > +#define UL_5G_LOAD_BALANCE 128 > +#define DL_5G_LOAD_BALANCE 128 > +#define FLR_5G_TIMEOUT 610 > +#endif > + > #define OPS_CACHE_SIZE 256U > #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */ > > @@ -587,6 +600,51 @@ typedef int (test_case_function)(struct active_device *ad, > info->dev_name); > } > #endif > +#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC > + if ((get_init_device() == true) && > + (!strcmp(info->drv.driver_name, FPGA_5GNR_PF_DRIVER_NAME))) { > + struct fpga_5gnr_fec_conf conf; > + unsigned int i; > + > + printf("Configure FPGA 5GNR FEC Driver %s with default values\n", > + info->drv.driver_name); > + > + /* clear default configuration before initialization */ > + memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf)); > + > + /* Set PF mode : > + * true if PF is used for data plane > + * false for VFs > + */ > + conf.pf_mode_en = true; > + > + for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) { > + /* Number of UL queues per VF (fpga supports 8 VFs) */ > + conf.vf_ul_queues_number[i] = VF_UL_5G_QUEUE_VALUE; > + /* Number of DL queues per VF (fpga supports 8 VFs) */ > + conf.vf_dl_queues_number[i] = VF_DL_5G_QUEUE_VALUE; > + } > + > + /* UL bandwidth. Needed for schedule algorithm */ > + conf.ul_bandwidth = UL_5G_BANDWIDTH; > + /* DL bandwidth */ > + conf.dl_bandwidth = DL_5G_BANDWIDTH; > + > + /* UL & DL load Balance Factor to 64 */ > + conf.ul_load_balance = UL_5G_LOAD_BALANCE; > + conf.dl_load_balance = DL_5G_LOAD_BALANCE; > + > + /**< FLR timeout value */ > + conf.flr_time_out = FLR_5G_TIMEOUT; > + > + /* setup FPGA PF with configuration information */ > + ret = fpga_5gnr_fec_configure(info->dev_name, &conf); > + TEST_ASSERT_SUCCESS(ret, > + "Failed to configure 5G FPGA PF for bbdev %s", > + info->dev_name); > + } > +#endif > + > nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues); > nb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES); >