[dpdk-dev] [disscussion] mlx4 driver MLX4_PMD_TX_MP_CACHE default vaule

[chenchanghu <chenchanghu@huawei.com>]

Hi,
         When I used the mlx4 pmd, I meet a problem about MLX4_PMD_TX_MP_CACHE vaule, which is used for Memory pool to Memory region translation. The detail test is descripted below.
1.Test environmemt infomation:
  a. Linux distribution: CentOS
  b. dpdk version: dpdk-16.04
  c. Ethernet device : mlx4 VF
  d. pmd info: mlx4 poll-mode-driver

2.Test diagram:
+----------------------+    +---------------------+         +-----------------------+
| client1       |    |  client2     |  .....    |  clientN      |
+----------------+----+    +-------+------------+         +----------+------------+
                  |         |                 |
                  |         |                 |
               +----v---------------v------------------------------v------+
               |              share memory queue   |
               +----------------------------+------------------------------+
                                |
                                |
             +-------------------------------v--------------------------------+
             |                    server            |
             +-------------------------------+--------------------------------+
                                |
                                |
             +-------------------------------v--------------------------------+
             |             dpdk rte_eth_tx_burst      |
             +-------------------------------+--------------------------------+
                                |
             +-------------------------------v---------------------------------+
             |                mlx4 pmd driver         |
             +-----------------------------------------------------------------+
  a. Every client has one memory pool, all clients send message to server queue in the shared memory.
  b. Server is only one thread, and mlx4 pmd use one tx queue.

3.Test step:
  a. We start 30 clients, which means total mempool number reaching 30, every client will send 20 packets/second, every packet length is 10k.However,the server will do large packet segmentation before the packet send to rte_eth_tx_burst.
  b. When we use the mlx4 pmd default MLX4_PMD_TX_MP_CACHE value which is 8, we found that the function 'rte_eth_tx_burst' cost about 40ms, which is mostly cost by the function 'ibv_reg_mr'.
  c. Then we modify the MLX4_PMD_TX_MP_CACHE vaule to 32, which is configured the vaule 'CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE' in the config/common_base file, we found the function 'rte_eth_tx_burst' running time is less than 5ms.

   Would the community modify the default CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE value to 32 to adapt the scenario like above description, avoiding the slow operation when use too many mempool number
which is more than the CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE value in one tx queue.
   Please send your reply to chenchanghu@huawei.com<mailto:chenchanghu@huawei.com>, any suggestion is to be greatefully appreciated.
4. Patch:
diff --git a/config/common_base b/config/common_base
index a0580d1..af6ba47 100644
--- a/config/common_base
+++ b/config/common_base
@@ -207,7 +207,7 @@ CONFIG_RTE_LIBRTE_MLX4_PMD=y
CONFIG_RTE_LIBRTE_MLX4_DEBUG=n
CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N=4
CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE=0
-CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8
+CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=32
CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS=1