From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 0980E5690 for ; Wed, 18 Mar 2015 14:20:53 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 18 Mar 2015 06:20:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,422,1422950400"; d="scan'208";a="681869887" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by fmsmga001.fm.intel.com with ESMTP; 18 Mar 2015 06:20:52 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.3.224.2; Wed, 18 Mar 2015 21:20:49 +0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.108]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.149]) with mapi id 14.03.0224.002; Wed, 18 Mar 2015 21:20:42 +0800 From: "Liu, Yong" To: "Qiu, Michael" , "thomas.monjalon@6wind.com" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported instruction `crc32' in i686 platform Thread-Index: AQHQWi4pA43dQGLIZkeSBRr5wmYb8J0iQ8Gw Date: Wed, 18 Mar 2015 13:20:41 +0000 Message-ID: <86228AFD5BCD8E4EBFD2B90117B5E81E10DA603B@SHSMSX103.ccr.corp.intel.com> References: <1425574530-16019-1-git-send-email-michael.qiu@intel.com> <1425880685-27424-1-git-send-email-michael.qiu@intel.com> In-Reply-To: <1425880685-27424-1-git-send-email-michael.qiu@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "yerden.zhumabekov@sts.kz" Subject: Re: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported instruction `crc32' in i686 platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Mar 2015 13:20:54 -0000 Michael & Thomas, Should we use software crc function replace of hardware crc function in 'cr= c32c_sse42_u64' when arch is i686? Thus application still can use CRC32_SSE42_x64 algorithm for crc calculatio= n when build with i686 configuration. This may helpful for simplify application code. > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Michael Qiu > Sent: Monday, March 09, 2015 1:58 PM > To: dev@dpdk.org > Cc: yerden.zhumabekov@sts.kz > Subject: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported > instruction `crc32' in i686 platform >=20 > CC rte_hash.o > Error: unsupported instruction `crc32' >=20 > The root cause is that i686 platform does not support 'crc32q' > Need make it only available in x86_64 platform >=20 > Signed-off-by: Michael Qiu > Acked-by: Yerden Zhumabekov > --- > v3 --> v2: > Add sub function for #else which returns 0 > v2 --> v1: > Make crc32 instruction only works in X86 platform >=20 > lib/librte_hash/rte_hash_crc.h | 46 +++++++++++++++++++++++++++++++++---= - > ----- > 1 file changed, 36 insertions(+), 10 deletions(-) >=20 > diff --git a/lib/librte_hash/rte_hash_crc.h > b/lib/librte_hash/rte_hash_crc.h > index d28bb2a..f1dbded 100644 > --- a/lib/librte_hash/rte_hash_crc.h > +++ b/lib/librte_hash/rte_hash_crc.h > @@ -47,6 +47,7 @@ extern "C" { > #include > #include > #include > +#include >=20 > /* Lookup tables for software implementation of CRC32C */ > static const uint32_t crc32c_tables[8][256] =3D {{ > @@ -364,6 +365,7 @@ crc32c_2words(uint64_t data, uint32_t init_val) > return crc; > } >=20 > +#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64) > static inline uint32_t > crc32c_sse42_u32(uint32_t data, uint32_t init_val) > { > @@ -375,16 +377,6 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val) > } >=20 > static inline uint32_t > -crc32c_sse42_u64(uint64_t data, uint64_t init_val) > -{ > - __asm__ volatile( > - "crc32q %[data], %[init_val];" > - : [init_val] "+r" (init_val) > - : [data] "rm" (data)); > - return init_val; > -} > - > -static inline uint32_t > crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) > { > union { > @@ -397,6 +389,40 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t > init_val) > init_val =3D crc32c_sse42_u32(d.u32[1], init_val); > return init_val; > } > +#else > +static inline uint32_t > +crc32c_sse42_u32(__rte_unused uint32_t data, > + __rte_unused uint32_t init_val) > +{ > + return 0; > +} > + > +static inline uint32_t > +crc32c_sse42_u64_mimic(__rte_unused uint32_t data, > + __rte_unused uint32_t init_val) > +{ > + return 0; > +} > +#endif > + > +#ifdef RTE_ARCH_X86_64 > +static inline uint32_t > +crc32c_sse42_u64(uint64_t data, uint64_t init_val) > +{ > + __asm__ volatile( > + "crc32q %[data], %[init_val];" > + : [init_val] "+r" (init_val) > + : [data] "rm" (data)); > + return init_val; > +} > +#else > +static inline uint32_t > +crc32c_sse42_u64(__rte_unused uint64_t data, > + __rte_unused uint64_t init_val) > +{ return crc32c_2words(data, init_val); > + return 0; > +} > +#endif >=20 > #define CRC32_SW (1U << 0) > #define CRC32_SSE42 (1U << 1) > -- > 1.9.3