From: Padam Jeet Singh <padam.singh@inventum.net>
To: "Liu, Jijiang" <jijiang.liu@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] Wrong TCP Checkum computed by hardware
Date: Wed, 28 Oct 2015 16:32:15 +0530 [thread overview]
Message-ID: <86D29314-5420-4E94-B925-41C1A001548E@inventum.net> (raw)
In-Reply-To: <1ED644BD7E0A5F4091CF203DAFB8E4CC22BC43AF@SHSMSX101.ccr.corp.intel.com>
>>
> Yes, you are correct, I just noticed you declare it is static, If possible, send more codes to me, I can help you with this.
>>>
>>>> Thanks,
>>>> Padam
>
I have the following code:
mbuf->ol_flags = (uint16_t) (mbuf->ol_flags &
(~PKT_TX_OFFLOAD_MASK));
mbuf->ol_flags |= PKT_TX_IP_CKSUM;
ipv4hdr->hdr_checksum = 0;
tcphdr = (struct tcp_hdr *)(pkt + sizeof(struct ether_hdr) +
sizeof(struct ipv4_hdr));
#ifdef L4CSUM_SW
tcphdr->cksum = 0;
tcphdr->cksum = get_ipv4_udptcp_checksum(ipv4hdr, (uint16_t*)tcphdr);
#else
mbuf->ol_flags |= PKT_TX_TCP_CKSUM;
if(!(mbuf->ol_flags & PKT_TX_IPV4))
mbuf->ol_flags |= PKT_TX_IPV4;
tcphdr->cksum = 0;
tcphdr->cksum = rte_ipv4_phdr_cksum(ipv4hdr);
#endif
mbuf->pkt.vlan_macip.f.vlan_tci = 100;
mbuf->ol_flags |= PKT_TX_VLAN_PKT;
I have added a macro called L4CSUM_SW, if enabled does L4 Checksum computation in software. When I enable this, the packet received has the correct TCP checksum. It is important to note that the checksum is being computed, but is being computed wrong when TX_VLAN, IP_CKSUM and TCP_CKSUM are enabled.
When I do the same test with VLAN removed from the setup, the TCP checksum computation is correct.
The system exhibiting this issue is a Intel(R) Xeon(R) CPU E5-2620 v3 @ 2.40GHz X 2, with 2 X 82599ES on a PCIe3 bus:
02:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit SFI/SFP+ Network Connection (rev 01)
Flags: bus master, fast devsel, latency 0, IRQ 32
Memory at c7d20000 (64-bit, non-prefetchable) [size=128K]
Memory at c7d44000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] MSI-X: Enable+ Count=64 Masked-
Capabilities: [a0] Express Endpoint, MSI 00
Capabilities: [e0] Vital Product Data
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Device Serial Number 00-90-0b-ff-ff-3f-19-d0
Capabilities: [150] Alternative Routing-ID Interpretation (ARI)
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
Kernel driver in use: igb_uio
Kernel modules: ixgbe
prev parent reply other threads:[~2015-10-28 11:02 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-28 6:50 Padam Jeet Singh
2015-10-28 6:57 ` Matthew Hall
2015-10-28 7:19 ` Padam Jeet Singh
2015-10-28 8:01 ` Liu, Jijiang
2015-10-28 8:12 ` Padam Jeet Singh
2015-10-28 8:16 ` Liu, Jijiang
2015-10-28 8:30 ` Padam Jeet Singh
2015-10-28 8:34 ` Liu, Jijiang
2015-10-28 11:02 ` Padam Jeet Singh [this message]
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