From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id D8895454EF;
Tue, 25 Jun 2024 13:30:24 +0200 (CEST)
Received: from mails.dpdk.org (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 2072142EA6;
Tue, 25 Jun 2024 13:21:13 +0200 (CEST)
Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19])
by mails.dpdk.org (Postfix) with ESMTP id 5F18D42FB2
for <dev@dpdk.org>; Tue, 25 Jun 2024 13:18:17 +0200 (CEST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
d=intel.com; i=@intel.com; q=dns/txt; s=Intel;
t=1719314297; x=1750850297;
h=from:to:cc:subject:date:message-id:in-reply-to:
references:mime-version:content-transfer-encoding;
bh=u5mgyvQKZnKiseTYCYzuPpT9O+EZ2XChh2pNjSP2oEg=;
b=BWiHDSqvRzAXNVw1vUIPPIfcOPycAqbWMKp5VjxO41jCuQAwvn95CW6S
AKY1fyCdNxLGU3k+3Ge0eQWN6Bh+HEkWfNWP4wq5fy3OdeX2AoY35EJPv
c4BU2L7yptdnK9GzHFZMMzdajf7I29fJCL95hQY14x/PmqliO6UDLMlha
wo5GHQg6Xqej8fnvAfVJNooKErpYY+tri/Idzqyt8zIHGrIjsCb6cV7MU
3IMbbMuCpneId1bridN6NCcqfMNliRdqrZaAijLYgRfZt6wGSKkTWZovY
3IAkwR/hGvhKOVLC69vRsnAb2HCR72ajg1c8EH9vls9uBiKH989gfB9jS A==;
X-CSE-ConnectionGUID: +IabUTyNRduKHXBeAie9xA==
X-CSE-MsgGUID: hXJPmisSR8SfYnZgd3+AmA==
X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080667"
X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080667"
Received: from orviesa009.jf.intel.com ([10.64.159.149])
by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
25 Jun 2024 04:18:16 -0700
X-CSE-ConnectionGUID: RS0yM6oWSDymdC0WrRefog==
X-CSE-MsgGUID: B4HAtbq2TsqmE6fXZ+oo3g==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719795"
Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167])
by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:16 -0700
From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: Milena Olech <milena.olech@intel.com>, bruce.richardson@intel.com,
ian.stokes@intel.com
Subject: [PATCH v3 122/129] net/ice/base: remove PHY port timer bypass mode
Date: Tue, 25 Jun 2024 12:14:07 +0100
Message-ID: <871c455605f3595f2613d4fc2fb7afd6a389ef42.1719313664.git.anatoly.burakov@intel.com>
X-Mailer: git-send-email 2.43.0
In-Reply-To: <cover.1719313663.git.anatoly.burakov@intel.com>
References: <cover.1718204528.git.anatoly.burakov@intel.com>
<cover.1719313663.git.anatoly.burakov@intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
From: Milena Olech <milena.olech@intel.com>
Previous implementation switches between bypass and Vernier mode
dynamically. However bypass mode should be removed due to low
precision.
Signed-off-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 195 +-----------------------------
drivers/net/ice/base/ice_ptp_hw.h | 6 +-
drivers/net/ice/ice_ethdev.c | 2 +-
3 files changed, 6 insertions(+), 197 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 70f3b2d3d1..2d042367a7 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2228,7 +2228,6 @@ ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
* ice_start_phy_timer_eth56g - Start the PHY clock timer
* @hw: pointer to the HW struct
* @port: the PHY port to start
- * @bypass: unused, for compatibility
*
* Start the clock of a PHY port. This must be done as part of the flow to
* re-calibrate Tx and Rx timestamping offsets whenever the clock time is
@@ -2236,7 +2235,7 @@ ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
*
*/
int
-ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
+ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
{
int err;
u32 lo, hi;
@@ -3887,47 +3886,6 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
return 0;
}
-/**
- * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Calculate and program the fixed Tx offset, and indicate that the offset is
- * ready. This can be used when operating in bypass mode.
- */
-static int
-ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
-{
- enum ice_ptp_link_spd link_spd;
- enum ice_ptp_fec_mode fec_mode;
- int err;
- u64 total_offset;
-
- err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (err)
- return err;
-
- total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
-
- /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
- * register, then indicate that the Tx offset is ready. After this,
- * timestamps will be enabled.
- *
- * Note that this skips including the more precise offsets generated
- * by the Vernier calibration.
- */
- err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
- total_offset);
- if (err)
- return err;
-
- err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
- if (err)
- return err;
-
- return 0;
-}
-
/**
* ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx
* @hw: pointer to the HW struct
@@ -4235,47 +4193,6 @@ static int ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw)
return 0;
}
-/**
- * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Calculate and program the fixed Rx offset, and indicate that the offset is
- * ready. This can be used when operating in bypass mode.
- */
-static int
-ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
-{
- enum ice_ptp_link_spd link_spd;
- enum ice_ptp_fec_mode fec_mode;
- int err;
- u64 total_offset;
-
- err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (err)
- return err;
-
- total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
-
- /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
- * register, then indicate that the Rx offset is ready. After this,
- * timestamps will be enabled.
- *
- * Note that this skips including the more precise offsets generated
- * by Vernier calibration.
- */
- err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
- total_offset);
- if (err)
- return err;
-
- err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
- if (err)
- return err;
-
- return 0;
-}
-
/**
* ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time
* @hw: pointer to the HW struct
@@ -4456,19 +4373,14 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
* ice_start_phy_timer_e822 - Start the PHY clock timer
* @hw: pointer to the HW struct
* @port: the PHY port to start
- * @bypass: if true, start the PHY in bypass mode
*
* Start the clock of a PHY port. This must be done as part of the flow to
* re-calibrate Tx and Rx timestamping offsets whenever the clock time is
* initialized or when link speed changes.
*
- * Bypass mode enables timestamps immediately without waiting for Vernier
- * calibration to complete. Hardware will still continue taking Vernier
- * measurements on Tx or Rx of packets, but they will not be applied to
- * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware
- * has completed offset calculation.
+ * Hardware will take Vernier measurements on Tx or Rx of packets.
*/
-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
+int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
{
u32 lo, hi, val;
u64 incval;
@@ -4549,23 +4461,6 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
if (err)
return err;
- if (bypass) {
- val |= P_REG_PS_BYPASS_MODE_M;
- /* Enter BYPASS mode, enabling timestamps immediately. */
- err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (err)
- return err;
-
- /* Program the fixed Tx offset */
- err = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
- if (err)
- return err;
-
- /* Program the fixed Rx offset */
- err = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
- if (err)
- return err;
- }
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
@@ -4607,90 +4502,6 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
return 0;
}
-/**
- * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * After hardware finishes vernier calculations for the Tx and Rx offset, this
- * function can be used to exit bypass mode by updating the total Tx and Rx
- * offsets, and then disabling bypass. This will enable hardware to include
- * the more precise offset calibrations, increasing precision of the generated
- * timestamps.
- *
- * This cannot be done until hardware has measured the offsets, which requires
- * waiting until at least one packet has been sent and received by the device.
- */
-int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
-{
- int err;
- u32 val;
-
- err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
- port, err);
- return err;
- }
-
- if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
- ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port %u\n",
- port);
- return ICE_ERR_NOT_READY;
- }
-
- err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
- port, err);
- return err;
- }
-
- if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
- ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port %u\n",
- port);
- return ICE_ERR_NOT_READY;
- }
-
- err = ice_phy_cfg_tx_offset_e822(hw, port);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, err %d\n",
- port, err);
- return err;
- }
-
- err = ice_phy_cfg_rx_offset_e822(hw, port);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, err %d\n",
- port, err);
- return err;
- }
-
- /* Exit bypass mode now that the offset has been updated */
- err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, err %d\n",
- port, err);
- return err;
- }
-
- if (!(val & P_REG_PS_BYPASS_MODE_M))
- ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n",
- port);
-
- val &= ~P_REG_PS_BYPASS_MODE_M;
- err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (err) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, err %d\n",
- port, err);
- return err;
- }
-
- ice_info(hw, "Exiting bypass mode on PHY port %u\n", port);
-
- return 0;
-}
-
/* E810 functions
*
* The following functions operate on the E810 series devices which use
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index 90db99327c..686246ab92 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -256,11 +256,9 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
int
ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
-int
-ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
+int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
-int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);
/* E810 family functions */
int ice_ptp_init_phy_e810(struct ice_hw *hw);
@@ -301,7 +299,7 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
int
ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
int
-ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass);
+ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 64ac64326a..dbdcacf019 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -2518,7 +2518,7 @@ ice_dev_init(struct rte_eth_dev *dev)
hw->phy_model = ICE_PHY_E822;
if (hw->phy_model == ICE_PHY_E822) {
- ret = ice_start_phy_timer_e822(hw, hw->pf_id, true);
+ ret = ice_start_phy_timer_e822(hw, hw->pf_id);
if (ret)
PMD_INIT_LOG(ERR, "Failed to start phy timer\n");
}
--
2.43.0