From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 201454404F; Wed, 12 Jun 2024 17:20:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 614B142F8F; Wed, 12 Jun 2024 17:06:14 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 10B4D42F77 for ; Wed, 12 Jun 2024 17:06:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204771; x=1749740771; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2M9VafUcEaZGSyhawC1bAZr6pDBLWpq7G9jN8B8QKC8=; b=O3SOy1VbADz2G1kwbH83II+d0qMbaFzmb8fGMYNgXO3du41lUm/63LM7 YEuzqFlfW/SxffhrLW336xKRGEInxzoSYlD/7mJWyLmxTYI92cRgfYAg0 XnooKFzCgXmmmbuRDMV9xPuxCBaNATbuJ9EJMBBp9lo7QQtaftv+WJPV9 X9q5ASSve3zpMC3sePQBUn9G0lE4be9436g4rWEDKGZmcDVc1LiE2CbJJ cyBp9/baMI0aFWoOnYg1XTVEr2gt+ZmWD+vElAn8QTkKOzZo5mqujN6vD mdaChFBKC4UlUWndGNnNBL9Kei5+S1Km1Tpk/v+yDTwhHBaLyXbuFwQnZ g==; X-CSE-ConnectionGUID: PGFte3uoSA68rFLwU3gAwQ== X-CSE-MsgGUID: IdOZxkyeSqG0QA83V3Bc2w== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459880" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459880" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:10 -0700 X-CSE-ConnectionGUID: vZtr+uRhRJGTj2HQuxc9Ig== X-CSE-MsgGUID: g8KFxYSUTLiXkXT0ct6xQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925831" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:09 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Karol Kolacinski Subject: [PATCH v2 105/148] net/ice/base: implement interface to reset timestamp memory Date: Wed, 12 Jun 2024 16:01:39 +0100 Message-ID: <8739d744df418864760ad8184f71936223f0fe84.1718204529.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes Add an interface to clear the timestamp memory block for E822 and ETH56G based devices. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 65 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 2 + 2 files changed, 67 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 07018279b6..1928d92b67 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1481,6 +1481,25 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) return 0; } +/** + * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block + * @hw: pointer to the HW struct + */ +static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) +{ + unsigned int port; + + for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + if (!(hw->ena_lports & BIT(port))) + continue; + + ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, + 0); + ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, + 0); + } +} + /** * ice_ptp_prep_port_phy_time_eth56g - Prepare one PHY port with initial time * @hw: pointer to the HW struct @@ -3002,6 +3021,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) return 0; } +/** + * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block + * @hw: pointer to the HW struct + * @quad: the quad to read from + * + * Clear all timestamps from the PHY quad block that is shared between the + * internal PHYs on the E822 devices. + */ +void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad) +{ + ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); + ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); +} + +/** + * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks + * @hw: pointer to the HW struct + */ +static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw) +{ + u8 quad; + + for (quad = 0; quad < ICE_MAX_QUAD; quad++) { + ice_ptp_reset_ts_memory_quad_e822(hw, quad); + } +} + /** * ice_ptp_set_vernier_wl - Set the window length for vernier calibration * @hw: pointer to the HW struct @@ -6049,6 +6095,25 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) return err; } +/** + * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks + * @hw: pointer to the HW struct + */ +void ice_ptp_reset_ts_memory(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_ETH56G: + ice_ptp_reset_ts_memory_eth56g(hw); + break; + case ICE_PHY_E822: + ice_ptp_reset_ts_memory_e822(hw); + break; + case ICE_PHY_E810: + default: + return; + } +} + /** * ice_ptp_init_phc - Initialize PTP hardware clock * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 952e7966a3..f20ce8cb0d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -142,6 +142,7 @@ int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx); +void ice_ptp_reset_ts_memory(struct ice_hw *hw); int ice_ptp_init_phc(struct ice_hw *hw); bool refsync_pin_id_valid(struct ice_hw *hw, u8 id); int @@ -165,6 +166,7 @@ ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval); int ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts); +void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad); int ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src); -- 2.43.0