From: Maxime Coquelin <maxime.coquelin@redhat.com>
To: Hernan Vargas <hernan.vargas@intel.com>,
dev@dpdk.org, gakhil@marvell.com, trix@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, stable@dpdk.org
Subject: Re: [PATCH v3 07/30] baseband/acc100: enforce additional check on FCW
Date: Fri, 14 Oct 2022 11:48:23 +0200 [thread overview]
Message-ID: <896f979c-7b99-a2c6-ca5b-db3ab19c48a3@redhat.com> (raw)
In-Reply-To: <20221012025346.204394-8-hernan.vargas@intel.com>
On 10/12/22 04:53, Hernan Vargas wrote:
> Enforce additional check on Frame Control Word validity and add stronger
> alignment for decompression mode.
>
> Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions")
> Cc: stable@dpdk.org
>
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
> drivers/baseband/acc/acc100_pmd.h | 1 +
> drivers/baseband/acc/acc_common.h | 1 +
> drivers/baseband/acc/rte_acc100_pmd.c | 51 ++++++++++++++++++++++++---
> 3 files changed, 48 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h
> index b325948904..28063b3db0 100644
> --- a/drivers/baseband/acc/acc100_pmd.h
> +++ b/drivers/baseband/acc/acc100_pmd.h
> @@ -87,6 +87,7 @@
> #define ACC100_HARQ_DDR (512 * 1)
> #define ACC100_PRQ_DDR_VER 0x10092020
> #define ACC100_DDR_TRAINING_MAX (5000)
> +#define ACC100_HARQ_ALIGN_COMP 256
>
> struct acc100_registry_addr {
> unsigned int dma_ring_dl5g_hi;
> diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h
> index b3ac9800d1..b18319c06d 100644
> --- a/drivers/baseband/acc/acc_common.h
> +++ b/drivers/baseband/acc/acc_common.h
> @@ -119,6 +119,7 @@
>
> #define ACC_ALGO_SPA 0
> #define ACC_ALGO_MSA 1
> +#define ACC_HARQ_ALIGN_64B 64
>
> /* Helper macro for logging */
> #define rte_acc_log(level, fmt, ...) \
> diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
> index 5e8ed78559..c1446b3721 100644
> --- a/drivers/baseband/acc/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc/rte_acc100_pmd.c
> @@ -1038,6 +1038,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
> uint16_t harq_index;
> uint32_t l;
> bool harq_prun = false;
> + uint32_t max_hc_in;
>
> fcw->qm = op->ldpc_dec.q_m;
> fcw->nfiller = op->ldpc_dec.n_filler;
> @@ -1087,8 +1088,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
> harq_in_length = op->ldpc_dec.harq_combined_input.length;
> if (fcw->hcin_decomp_mode > 0)
> harq_in_length = harq_in_length * 8 / 6;
> - harq_in_length = RTE_ALIGN(harq_in_length, 64);
> - if ((harq_layout[harq_index].offset > 0) & harq_prun) {
> + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
> + - op->ldpc_dec.n_filler);
> + /* Alignment on next 64B - Already enforced from HC output */
> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B);
> + /* Stronger alignment requirement when in decompression mode */
> + if (fcw->hcin_decomp_mode > 0)
> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP);
> + if ((harq_layout[harq_index].offset > 0) && harq_prun) {
New lines in the above chunk would provide more clarity.
This is very packed.
> rte_bbdev_log_debug("HARQ IN offset unexpected for now\n");
> fcw->hcin_size0 = harq_layout[harq_index].size0;
> fcw->hcin_offset = harq_layout[harq_index].offset;
> @@ -1104,6 +1111,20 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
> fcw->hcin_offset = 0;
> fcw->hcin_size1 = 0;
> }
> + /* Enforce additional check on FCW validity */
> + max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC_HARQ_ALIGN_64B);
> + if ((fcw->hcin_size0 > max_hc_in) ||
> + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) ||
> + ((fcw->hcin_size0 > fcw->hcin_offset) &&
> + (fcw->hcin_size1 != 0))) {
> + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d",
> + fcw->hcin_size0, fcw->hcin_size1,
> + fcw->hcin_offset,
> + fcw->ncb, fcw->nfiller);
> + /* Disable HARQ input in that case to carry forward */
> + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> + fcw->hcin_en = 0;
> + }
>
> fcw->itmax = op->ldpc_dec.iter_max;
> fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> @@ -1132,10 +1153,19 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
> k0_p = (fcw->k0 > parity_offset) ?
> fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> - l = k0_p + fcw->rm_e;
> + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> harq_out_length = (uint16_t) fcw->hcin_size0;
> - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p);
> - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0;
> + harq_out_length = RTE_MAX(harq_out_length, l);
> + /* Stronger alignment when in compression mode */
> + if (fcw->hcout_comp_mode > 0)
> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP);
> + /* Cannot exceed the pruned Ncb circular buffer */
> + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> + /* Alignment on next 64B */
> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC_HARQ_ALIGN_64B);
> + /* Stronger alignment when in compression mode enforced again */
> + if (fcw->hcout_comp_mode > 0)
> + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP);
Same here, this is very packed.
> if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) &&
> harq_prun) {
> fcw->hcout_size0 = (uint16_t) fcw->hcin_size0;
> @@ -1146,6 +1176,13 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
> fcw->hcout_size1 = 0;
> fcw->hcout_offset = 0;
> }
> + if (fcw->hcout_size0 == 0) {
> + rte_bbdev_log(ERR, " Invalid FCW : HCout %d",
> + fcw->hcout_size0);
> + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
> + fcw->hcout_en = 0;
> + }
> +
> harq_layout[harq_index].offset = fcw->hcout_offset;
> harq_layout[harq_index].size0 = fcw->hcout_size0;
> } else {
> @@ -1186,6 +1223,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
> /* Disable HARQ input in that case to carry forward */
> op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> }
> + if (unlikely(fcw->rm_e == 0)) {
> + rte_bbdev_log(WARNING, "Null E input provided");
> + fcw->rm_e = 2;
> + }
>
> fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
next prev parent reply other threads:[~2022-10-14 9:48 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 2:53 [PATCH v3 00/30] baseband/acc100: changes for 22.11 Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 01/30] baseband/acc100: fix ring availability calculation Hernan Vargas
2022-10-14 9:18 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 02/30] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-10-14 9:25 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 03/30] baseband/acc100: memory leak fix Hernan Vargas
2022-10-14 9:29 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 04/30] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-10-14 9:33 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 05/30] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-10-14 9:35 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 06/30] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-10-14 9:39 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 07/30] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-10-14 9:48 ` Maxime Coquelin [this message]
2022-10-12 2:53 ` [PATCH v3 08/30] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-10-14 9:55 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 09/30] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-10-14 9:56 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 10/30] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-10-14 9:56 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 11/30] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-10-14 10:02 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 12/30] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 13/30] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 14/30] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 15/30] baseband/acc100: add enqueue status Hernan Vargas
2022-10-14 10:04 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 16/30] baseband/acc100: add scatter-gather support Hernan Vargas
2022-10-14 10:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 17/30] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-10-14 10:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 18/30] baseband/acc100: enable input validation by default Hernan Vargas
2022-10-13 12:56 ` [EXT] " Akhil Goyal
2022-10-18 16:28 ` Maxime Coquelin
2022-10-19 22:12 ` Chautru, Nicolas
2022-10-21 8:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 19/30] baseband/acc100: added LDPC transport block support Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 20/30] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 21/30] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 22/30] baseband/acc100: add queue stop operation Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 23/30] baseband/acc100: update uplink CB input length Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 24/30] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-10-13 13:04 ` [EXT] " Akhil Goyal
2022-10-12 2:53 ` [PATCH v3 25/30] baseband/acc100: update log messages Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 26/30] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 27/30] baseband/acc100: update device info Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 28/30] baseband/acc100: add ring companion address Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 29/30] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-10-13 13:09 ` [EXT] " Akhil Goyal
2022-10-12 2:53 ` [PATCH v3 30/30] baseband/acc100: configure PMON control registers Hernan Vargas
2022-10-13 8:28 ` [EXT] [PATCH v3 00/30] baseband/acc100: changes for 22.11 Akhil Goyal
2022-10-13 13:01 ` Akhil Goyal
2022-10-14 2:46 ` Chautru, Nicolas
2022-10-14 6:33 ` Akhil Goyal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=896f979c-7b99-a2c6-ca5b-db3ab19c48a3@redhat.com \
--to=maxime.coquelin@redhat.com \
--cc=dev@dpdk.org \
--cc=gakhil@marvell.com \
--cc=hernan.vargas@intel.com \
--cc=nicolas.chautru@intel.com \
--cc=qi.z.zhang@intel.com \
--cc=stable@dpdk.org \
--cc=trix@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).