From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id EC4A8CFFE for ; Wed, 29 Mar 2017 17:11:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490800262; x=1522336262; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=TEKHXbkVwlvtW68+rRTu+Ot6kVhXkn8dKOebi5E2pyw=; b=w5wE/i4u5ucQ4yOHvjgsTiq1eAQ6drOJrIA/jgkC+GmmpDqqRG5/t+w0 0D0bqd2WgACIGnUUsRY/Jkn1jAEo3g==; Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2017 08:10:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,241,1486454400"; d="scan'208";a="81918941" Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by fmsmga005.fm.intel.com with ESMTP; 29 Mar 2017 08:10:34 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.239]) by IRSMSX106.ger.corp.intel.com ([169.254.8.202]) with mapi id 14.03.0319.002; Wed, 29 Mar 2017 16:10:33 +0100 From: "Iremonger, Bernard" To: "Lu, Wenzhuo" , "dev@dpdk.org" , "Xing, Beilei" , "Wu, Jingjing" CC: "Zhang, Helin" Thread-Topic: [PATCH v3 2/5] net/i40e: parse QinQ pattern Thread-Index: AQHSp99bw6Lx0q3VsEGko5wsH8G20aGq9hEAgAD2G8A= Date: Wed, 29 Mar 2017 15:10:32 +0000 Message-ID: <8CEF83825BEC744B83065625E567D7C224D4C73F@IRSMSX108.ger.corp.intel.com> References: <1490287113-8895-1-git-send-email-bernard.iremonger@intel.com> <1490718059-380-3-git-send-email-bernard.iremonger@intel.com> <6A0DE07E22DDAD4C9103DF62FEBC09093B583FA8@shsmsx102.ccr.corp.intel.com> In-Reply-To: <6A0DE07E22DDAD4C9103DF62FEBC09093B583FA8@shsmsx102.ccr.corp.intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjI3ZTVkODYtODBlYS00YmVkLThjM2EtZGY2YTBjNzJhM2QzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6ImYzUnJ2Nll2TUg2Vk5WNTl3MmtlcUdQQXBISlVHUm0xSnZwN29IZ2pCKzA9In0= x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 2/5] net/i40e: parse QinQ pattern X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Mar 2017 15:11:02 -0000 Hi Wenzhuo, > -----Original Message----- > From: Lu, Wenzhuo > Sent: Wednesday, March 29, 2017 2:25 AM > To: Iremonger, Bernard ; dev@dpdk.org; > Xing, Beilei ; Wu, Jingjing > Cc: Zhang, Helin > Subject: RE: [PATCH v3 2/5] net/i40e: parse QinQ pattern >=20 > Hi Bernard, >=20 > > -----Original Message----- > > From: Iremonger, Bernard > > Sent: Wednesday, March 29, 2017 12:21 AM > > To: dev@dpdk.org; Xing, Beilei; Wu, Jingjing > > Cc: Zhang, Helin; Lu, Wenzhuo; Iremonger, Bernard > > Subject: [PATCH v3 2/5] net/i40e: parse QinQ pattern > > > > add QinQ pattern. > > add i40e_flow_parse_qinq_pattern function. > > add i40e_flow_parse_qinq_filter function. > > > > Signed-off-by: Bernard Iremonger > > --- > > drivers/net/i40e/i40e_flow.c | 187 > > ++++++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 185 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.= c > index > > be243e172..39b09ead5 100644 > > --- a/drivers/net/i40e/i40e_flow.c > > +++ b/drivers/net/i40e/i40e_flow.c >=20 > > + /* Check specification and mask to get the filter type */ > > + if (vlan_spec && vlan_mask && > The previous code already checked the vlan_spec and vlan_mask should not > be NULL. Seems not necessary to check it again. I will remove this check. > > + (vlan_mask->tci =3D=3D rte_cpu_to_be_16(I40E_TCI_MASK))) { > The vlan_mask here should be inner vlan mask. The outer vlan mask is los= t. > Should we store the outer vlan mask and check it? Yes, I will store and check both inner and outer vlan masks. =20 > > + /* There is an inner and outer vlan */ > > + filter->outer_vlan =3D rte_be_to_cpu_16(o_vlan_spec->tci) > > + & I40E_TCI_MASK; > > + filter->inner_vlan =3D rte_be_to_cpu_16(i_vlan_spec->tci) > > + & I40E_TCI_MASK; > > + if (i_eth_spec && i_eth_mask) > > + filter->filter_type =3D > > + I40E_TUNNEL_FILTER_CUSTOM_QINQ; > > + else { > > + rte_flow_error_set(error, EINVAL, > > + RTE_FLOW_ERROR_TYPE_ITEM, > > + NULL, > > + "Invalid filter type"); > > + return -rte_errno; > > + } > > + } else if ((!vlan_spec && !vlan_mask) || > > + (vlan_spec && vlan_mask && vlan_mask->tci =3D=3D 0x0)) { > > + if (i_eth_spec && i_eth_mask) { > The similar concern as above. I will change as above. =20 >=20 > > + filter->filter_type =3D > > I40E_TUNNEL_FILTER_CUSTOM_QINQ; > > + } else { > > + rte_flow_error_set(error, EINVAL, > > + RTE_FLOW_ERROR_TYPE_ITEM, NULL, > > + "Invalid filter type"); > > + return -rte_errno; > > + } > > + } else { > > + rte_flow_error_set(error, EINVAL, > > + RTE_FLOW_ERROR_TYPE_ITEM, NULL, > > + "Not supported by tunnel filter."); > > + return -rte_errno; > > + } > > + > > + filter->tunnel_type =3D I40E_TUNNEL_TYPE_QINQ; > > + > > + return 0; > > +} Regards, Bernard.