From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id A59D9DE0 for ; Fri, 31 Mar 2017 10:01:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490947311; x=1522483311; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=SCPgCxvD7NMDAwK/LOukLwfPVcV63tRYB/Dz7a+rEPw=; b=J0U8Ij7aJK7PYAAGegNhIX0GlAiSTeTYvsiPUaCjD/+oaccfUR/nS/0y aIJ/gROWldmrb3TnMBkL4cs1tDJtvQ==; Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2017 01:01:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,251,1486454400"; d="scan'208";a="81287045" Received: from irsmsx105.ger.corp.intel.com ([163.33.3.28]) by orsmga005.jf.intel.com with ESMTP; 31 Mar 2017 01:01:49 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.239]) by irsmsx105.ger.corp.intel.com ([169.254.7.163]) with mapi id 14.03.0319.002; Fri, 31 Mar 2017 09:01:48 +0100 From: "Iremonger, Bernard" To: "Lu, Wenzhuo" , "dev@dpdk.org" , "Xing, Beilei" , "Wu, Jingjing" CC: "Zhang, Helin" Thread-Topic: [PATCH v5 3/5] net/i40e: parse QinQ pattern Thread-Index: AQHSqXAskM84LBfOn0SNopGa7p35HKGuEDQAgACGdWA= Date: Fri, 31 Mar 2017 08:01:47 +0000 Message-ID: <8CEF83825BEC744B83065625E567D7C224D4DA3F@IRSMSX108.ger.corp.intel.com> References: <1490889702-15473-1-git-send-email-bernard.iremonger@intel.com> <1490890196-23795-4-git-send-email-bernard.iremonger@intel.com> <6A0DE07E22DDAD4C9103DF62FEBC09093B5855F7@shsmsx102.ccr.corp.intel.com> In-Reply-To: <6A0DE07E22DDAD4C9103DF62FEBC09093B5855F7@shsmsx102.ccr.corp.intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTUxZDVjNzItODIxMi00NjQ4LTkwOTAtNzg1YjdkNTJkNTgyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IktwT3FwTVwvK3hjT3Q2djNLNGRMY20rVDlyeXR3ajZzUTliUmphT0dQU3djPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v5 3/5] net/i40e: parse QinQ pattern X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Mar 2017 08:01:52 -0000 Hi Wenzhuo, > -----Original Message----- > From: Lu, Wenzhuo > Sent: Friday, March 31, 2017 1:59 AM > To: Iremonger, Bernard ; dev@dpdk.org; > Xing, Beilei ; Wu, Jingjing > Cc: Zhang, Helin > Subject: RE: [PATCH v5 3/5] net/i40e: parse QinQ pattern >=20 > Hi Bernard, >=20 > > -----Original Message----- > > From: Iremonger, Bernard > > Sent: Friday, March 31, 2017 12:10 AM > > To: dev@dpdk.org; Xing, Beilei; Wu, Jingjing > > Cc: Zhang, Helin; Lu, Wenzhuo; Iremonger, Bernard > > Subject: [PATCH v5 3/5] net/i40e: parse QinQ pattern > > > > add QinQ pattern. > > add i40e_flow_parse_qinq_pattern function. > > add i40e_flow_parse_qinq_filter function. > > > > Signed-off-by: Bernard Iremonger > > --- > > drivers/net/i40e/i40e_flow.c | 145 > > ++++++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 143 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/i40e/i40e_flow.c > > b/drivers/net/i40e/i40e_flow.c index dc456c338..bbec7dc1c 100644 > > --- a/drivers/net/i40e/i40e_flow.c > > +++ b/drivers/net/i40e/i40e_flow.c > > @@ -1,7 +1,7 @@ > > /*- > > * BSD LICENSE > > * > > - * Copyright (c) 2016 Intel Corporation. All rights reserved. > > + * Copyright (c) 2016-2017 Intel Corporation. All rights reserved. > > * > > * Redistribution and use in source and binary forms, with or withou= t > > * modification, are permitted provided that the following condition= s > > @@ -127,6 +127,18 @@ static int i40e_flow_destroy_tunnel_filter(struct > > i40e_pf *pf, static int i40e_flow_flush_fdir_filter(struct i40e_pf > > *pf); static int i40e_flow_flush_ethertype_filter(struct i40e_pf > > *pf); static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf); > > +static int > > +i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, > > + const struct rte_flow_attr *attr, > > + const struct rte_flow_item pattern[], > > + const struct rte_flow_action actions[], > > + struct rte_flow_error *error, > > + union i40e_filter_t *filter); static int > > +i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, > > + const struct rte_flow_item *pattern, > > + struct rte_flow_error *error, > > + struct i40e_tunnel_filter_conf *filter); > > > > const struct rte_flow_ops i40e_flow_ops =3D { > > .validate =3D i40e_flow_validate, > > @@ -317,6 +329,14 @@ static enum rte_flow_item_type pattern_mpls_4[] > =3D > > { > > RTE_FLOW_ITEM_TYPE_END, > > }; > > > > +/* Pattern matched QINQ */ > > +static enum rte_flow_item_type pattern_qinq_1[] =3D { > > + RTE_FLOW_ITEM_TYPE_ETH, > > + RTE_FLOW_ITEM_TYPE_VLAN, > > + RTE_FLOW_ITEM_TYPE_VLAN, > > + RTE_FLOW_ITEM_TYPE_END, > > +}; > > + > > static struct i40e_valid_pattern i40e_supported_patterns[] =3D { > > /* Ethertype */ > > { pattern_ethertype, i40e_flow_parse_ethertype_filter }, @@ -347,6 > > +367,8 @@ static struct i40e_valid_pattern i40e_supported_patterns[] = =3D > > +{ > > { pattern_mpls_2, i40e_flow_parse_mpls_filter }, > > { pattern_mpls_3, i40e_flow_parse_mpls_filter }, > > { pattern_mpls_4, i40e_flow_parse_mpls_filter }, > > + /* QINQ */ > > + { pattern_qinq_1, i40e_flow_parse_qinq_filter }, > > }; > > > > #define NEXT_ITEM_OF_ACTION(act, actions, index) = \ > > @@ -1170,7 +1192,7 @@ i40e_flow_parse_fdir_filter(struct rte_eth_dev > > *dev, > > return 0; > > } > > > > -/* Parse to get the action info of a tunnle filter > > +/* Parse to get the action info of a tunnel filter > > * Tunnel action only supports PF, VF and QUEUE. > > */ > > static int > > @@ -1719,6 +1741,125 @@ i40e_flow_parse_mpls_filter(struct > rte_eth_dev > > *dev, } > > > > static int > > +i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, > > + const struct rte_flow_item *pattern, > > + struct rte_flow_error *error, > > + struct i40e_tunnel_filter_conf *filter) { > > + const struct rte_flow_item *item =3D pattern; > > + const struct rte_flow_item_eth *eth_spec; > > + const struct rte_flow_item_eth *eth_mask; > > + const struct rte_flow_item_vlan *vlan_spec =3D NULL; > > + const struct rte_flow_item_vlan *vlan_mask =3D NULL; > > + const struct rte_flow_item_vlan *i_vlan_spec =3D NULL; > > + const struct rte_flow_item_vlan *i_vlan_mask =3D NULL; > > + const struct rte_flow_item_vlan *o_vlan_spec =3D NULL; > > + const struct rte_flow_item_vlan *o_vlan_mask =3D NULL; > > + > > + enum rte_flow_item_type item_type; > > + bool vlan_flag =3D 0; > > + > > + for (; item->type !=3D RTE_FLOW_ITEM_TYPE_END; item++) { > > + if (item->last) { > > + rte_flow_error_set(error, EINVAL, > > + RTE_FLOW_ERROR_TYPE_ITEM, > > + item, > > + "Not support range"); > > + return -rte_errno; > > + } > > + item_type =3D item->type; > > + switch (item_type) { > > + case RTE_FLOW_ITEM_TYPE_ETH: > > + eth_spec =3D (const struct rte_flow_item_eth *)item- > > >spec; > > + eth_mask =3D (const struct rte_flow_item_eth *)item- > > >mask; > > + if (eth_spec && eth_mask) { > Should it be (eth_spec || eth_mask)? > All the other is good to me. No, I believe this is correct ( I tested it and it worked correctly). >=20 > > + rte_flow_error_set(error, EINVAL, > > + > > RTE_FLOW_ERROR_TYPE_ITEM, > > + item, > > + "Invalid ether spec/mask"); > > + return -rte_errno; > > + } > > + break; Regards, Bernard.