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From: "Wang, Zhihong" <zhihong.wang@intel.com>
To: Ravi Kerur <rkerur@gmail.com>, "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v1 1/2] rte_memcmp functions using Intel AVX and	SSE intrinsics
Date: Thu, 26 May 2016 08:57:30 +0000	[thread overview]
Message-ID: <8F6C2BD409508844A0EFC19955BE094110743936@SHSMSX103.ccr.corp.intel.com> (raw)
In-Reply-To: <1457391644-29645-1-git-send-email-rkerur@gmail.com>



> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Ravi Kerur
> Sent: Tuesday, March 8, 2016 7:01 AM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH v1 1/2] rte_memcmp functions using Intel AVX and
> SSE intrinsics
> 
> v1:
>         This patch adds memcmp functionality using AVX and SSE
>         intrinsics provided by Intel. For other architectures
>         supported by DPDK regular memcmp function is used.
> 
>         Compiled and tested on Ubuntu 14.04(non-NUMA) and 15.10(NUMA)
>         systems.
> 
[...]

> +	if (unlikely(!_mm_testz_si128(xmm2, xmm2))) {
> +		__m128i idx =
> +			_mm_setr_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);

line over 80 characters ;)

> +
> +		/*
> +		 * Reverse byte order
> +		 */
> +		xmm0 = _mm_shuffle_epi8(xmm0, idx);
> +		xmm1 = _mm_shuffle_epi8(xmm1, idx);
> +
> +		/*
> +		* Compare unsigned bytes with instructions for signed bytes
> +		*/
> +		xmm0 = _mm_xor_si128(xmm0, _mm_set1_epi8(0x80));
> +		xmm1 = _mm_xor_si128(xmm1, _mm_set1_epi8(0x80));
> +
> +		return _mm_movemask_epi8(xmm0 > xmm1) -
> _mm_movemask_epi8(xmm1 > xmm0);
> +	}
> +
> +	return 0;
> +}

[...]

> +static inline int
> +rte_memcmp(const void *_src_1, const void *_src_2, size_t n)
> +{
> +	const uint8_t *src_1 = (const uint8_t *)_src_1;
> +	const uint8_t *src_2 = (const uint8_t *)_src_2;
> +	int ret = 0;
> +
> +	if (n < 16)
> +		return rte_memcmp_regular(src_1, src_2, n);
[...]
> +
> +	while (n > 512) {
> +		ret = rte_cmp256(src_1 + 0 * 256, src_2 + 0 * 256);

Thanks for the great work!

Seems to me there's a big improvement area before going into detailed
instruction layout tuning that -- No unalignment handling here for large
size memcmp.

So almost without a doubt the performance will be low in micro-architectures
like Sandy Bridge if the start address is unaligned, which might be a
common case.

> +		if (unlikely(ret != 0))
> +			return ret;
> +
> +		ret = rte_cmp256(src_1 + 1 * 256, src_2 + 1 * 256);
> +		if (unlikely(ret != 0))
> +			return ret;
> +
> +		src_1 = src_1 + 512;
> +		src_2 = src_2 + 512;
> +		n -= 512;
> +	}
> +	goto CMP_BLOCK_LESS_THAN_512;
> +}
> +
> +#else /* RTE_MACHINE_CPUFLAG_AVX2 */

  parent reply	other threads:[~2016-05-26  9:06 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-07 22:59 [dpdk-dev] [PATCH v1 0/2] rte_memcmp functions Ravi Kerur
2016-03-07 23:00 ` [dpdk-dev] [PATCH v1 1/2] rte_memcmp functions using Intel AVX and SSE intrinsics Ravi Kerur
2016-03-07 23:00   ` [dpdk-dev] [PATCH v1 2/2] Test cases for rte_memcmp functions Ravi Kerur
2016-05-26  9:05     ` Wang, Zhihong
2016-06-06 18:31       ` Ravi Kerur
2016-06-07 11:09         ` Wang, Zhihong
2017-01-02 20:41           ` Thomas Monjalon
2017-01-09  5:29             ` Wang, Zhihong
2017-01-09 11:08               ` Thomas Monjalon
2017-01-11  1:28                 ` Wang, Zhihong
2016-05-25  8:56   ` [dpdk-dev] [PATCH v1 1/2] rte_memcmp functions using Intel AVX and SSE intrinsics Thomas Monjalon
2016-05-26  8:57   ` Wang, Zhihong [this message]
2018-12-20 23:30     ` Ferruh Yigit

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