From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3494A09E9; Tue, 15 Dec 2020 04:00:45 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 313301E35; Tue, 15 Dec 2020 04:00:44 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 5E7C71E2F for ; Tue, 15 Dec 2020 04:00:42 +0100 (CET) IronPort-SDR: RtvUkxN8PyWdVcOLXJ+FLBpxJUKhnEHKEuPHpaiQDdBZ5LRkD+2GeS3oCKBIePLOb6XMtfysaN BOHt4L8vls5w== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="154624341" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="log'?scan'208";a="154624341" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 19:00:39 -0800 IronPort-SDR: sHL8NBeSmvnWCXXWnrVmVBSCD7oXCN13LgS8AvQqk8cxvVUUOvu3VMfKKDi5WLIh7Q1WZZNQhT 7hiZVTlOxs4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="log'?scan'208";a="411529918" Received: from fmsmsx604.amr.corp.intel.com ([10.18.126.84]) by orsmga001.jf.intel.com with ESMTP; 14 Dec 2020 19:00:39 -0800 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 14 Dec 2020 19:00:38 -0800 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by SHSMSX605.ccr.corp.intel.com (10.109.6.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 15 Dec 2020 11:00:36 +0800 Received: from shsmsx606.ccr.corp.intel.com ([10.109.6.216]) by SHSMSX606.ccr.corp.intel.com ([10.109.6.216]) with mapi id 15.01.1713.004; Tue, 15 Dec 2020 11:00:36 +0800 From: "Zhou, JunX W" To: "Yu, DapengX" , "Guo, Jia" CC: "dev@dpdk.org" , "Yu, DapengX" , "Zhang, Qi Z" Thread-Topic: [dpdk-dev] [PATCH] net/ixgbe: fix fdirctrl register setting Thread-Index: AQHWz135udw4h0cJrESqqF73GPEvnqn3fecA Date: Tue, 15 Dec 2020 03:00:36 +0000 Message-ID: <8aca632d412e494888896f24bb8ee4d9@intel.com> References: <20201211013506.49885-1-dapengx.yu@intel.com> In-Reply-To: <20201211013506.49885-1-dapengx.yu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.36] MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix fdirctrl register setting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Tested-by: Zhou, Jun -----Original Message----- From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of dapengx.yu@intel.com Sent: Friday, December 11, 2020 9:35 AM To: Guo, Jia Cc: dev@dpdk.org; Yu, DapengX ; Zhang, Qi Z Subject: [dpdk-dev] [PATCH] net/ixgbe: fix fdirctrl register setting From: YU DAPENG The function ixgbe_fdir_set_flexbytes_offset is used when create FDir rule = for flexbytes. It set a register: FDIRCTRL.FLEX_OFFSET, which cause that ev= en if the FDir flexbytes rule is destroyed, the rule still direct the packe= t and transfer it to the wrong place. It is because Setting FDIRCTRL shall = only be permitted on Flow Director initialization flow or Clearing the Flow= Director table, otherwise unexpected happens. In order to evade the limit,= add code to make setting FDIRCTRL work without unexpected effects. Fixes: f35fec63dde1 ("net/ixgbe: enable flex bytes for generic flow API") Cc: qi.z.zhang@intel.com Signed-off-by: YU DAPENG --- drivers/net/ixgbe/ixgbe_fdir.c | 23 +++++++++++++++++++++++ drivers/net/i= xgbe/ixgbe_flow.c | 7 +++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.= c index a0fab5070..56dddd56b 100644 --- a/drivers/net/ixgbe/ixgbe_fdir.c +++ b/drivers/net/ixgbe/ixgbe_fdir.c @@ -503,9 +503,32 @@ ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *de= v, uint16_t offset) { struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_hw_fdir_info *fdir_info =3D + IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); uint32_t fdirctrl; int i; =20 + if (fdir_info->flex_bytes_offset =3D=3D offset) + return 0; + + fdir_info->flex_bytes_offset =3D offset; + + /* + * 82599 adapters flow director init flow cannot be restarted, + * Workaround 82599 silicon errata by performing the following steps + * before re-writing the FDIRCTRL control register with the same value. + * - write 1 to bit 8 of FDIRCMD register & + * - write 0 to bit 8 of FDIRCMD register + */ + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | + IXGBE_FDIRCMD_CLEARHT)); + IXGBE_WRITE_FLUSH(hw); + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & + ~IXGBE_FDIRCMD_CLEARHT)); + IXGBE_WRITE_FLUSH(hw); + fdirctrl =3D IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); =20 fdirctrl &=3D ~IXGBE_FDIRCTRL_FLEX_MASK; diff --git a/drivers/net/ixgbe/i= xgbe_flow.c b/drivers/net/ixgbe/ixgbe_flow.c index 39f6ed73f..b37541d9b 100= 644 --- a/drivers/net/ixgbe/ixgbe_flow.c +++ b/drivers/net/ixgbe/ixgbe_flow.c @@ -3137,8 +3137,6 @@ ixgbe_flow_create(struct rte_eth_dev *dev, rte_memcpy(&fdir_info->mask, &fdir_rule.mask, sizeof(struct ixgbe_hw_fdir_mask)); - fdir_info->flex_bytes_offset =3D - fdir_rule.flex_bytes_offset; =20 if (fdir_rule.mask.flex_bytes_mask) ixgbe_fdir_set_flexbytes_offset(dev, @@ -3161,8 +3159,9 @@ ixgbe_flow_create(struct rte_eth_dev *dev, if (ret) goto out; =20 - if (fdir_info->flex_bytes_offset !=3D - fdir_rule.flex_bytes_offset) + if (fdir_rule.mask.flex_bytes_mask && + (fdir_info->flex_bytes_offset !=3D + fdir_rule.flex_bytes_offset)) goto out; } } -- 2.26.2.windows.1