From: Ferruh Yigit <ferruh.yigit@intel.com>
To: Suanming Mou <suanmingm@mellanox.com>,
viacheslavo@mellanox.com, matan@mellanox.com
Cc: rasland@mellanox.com, dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH v2 2/3] common/mlx5: add counter batch query ID alignment define
Date: Wed, 22 Jul 2020 14:22:42 +0100 [thread overview]
Message-ID: <8cc3a121-bc54-2dd0-1334-bd17ae3c54a0@intel.com> (raw)
In-Reply-To: <1595404727-164521-2-git-send-email-suanmingm@mellanox.com>
On 7/22/2020 8:58 AM, Suanming Mou wrote:
> The counter batch query requires ID to be aligned with 4.
>
> Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
> Acked-by: Matan Azrad <matan@mellanox.com>
> ---
> drivers/common/mlx5/mlx5_prm.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
> index cb5f968..8565d25 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -818,6 +818,9 @@ enum {
> */
> #define MLX5_CNT_BATCH_OFFSET 0x800000
>
> +/* The counter batch query requires ID align with 4. */
> +#define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
> +
> /* Flow counters. */
> struct mlx5_ifc_alloc_flow_counter_out_bits {
> u8 status[0x8];
>
Having only macro separated from usage is not very helpful, squashing this
commit with 3/3 where the macro is used in 'next-net' repo.
next prev parent reply other threads:[~2020-07-22 13:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 12:40 [dpdk-dev] [PATCH] net/mlx5: avoid invalid counter query Suanming Mou
2020-07-22 7:58 ` [dpdk-dev] [PATCH v2 1/3] net/mlx5: separate aging counter pool range Suanming Mou
2020-07-22 7:58 ` [dpdk-dev] [PATCH v2 2/3] common/mlx5: add counter batch query ID alignment define Suanming Mou
2020-07-22 13:22 ` Ferruh Yigit [this message]
2020-07-22 7:58 ` [dpdk-dev] [PATCH v2 3/3] net/mlx5: fix invalid counter query Suanming Mou
2020-07-22 11:35 ` [dpdk-dev] [PATCH v2 1/3] net/mlx5: separate aging counter pool range Raslan Darawsheh
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