From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 638531DBC for ; Mon, 23 Apr 2018 19:45:52 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Apr 2018 10:45:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,319,1520924400"; d="scan'208";a="49254662" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.42]) ([10.237.221.42]) by fmsmga001.fm.intel.com with ESMTP; 23 Apr 2018 10:45:49 -0700 To: Qi Zhang , thomas@monjalon.net Cc: konstantin.ananyev@intel.com, dev@dpdk.org, beilei.xing@intel.com, jingjing.wu@intel.com, wenzhuo.lu@intel.com References: <20180212045314.171616-1-qi.z.zhang@intel.com> <20180422115824.105219-1-qi.z.zhang@intel.com> <20180422115824.105219-4-qi.z.zhang@intel.com> From: Ferruh Yigit Openpgp: preference=signencrypt Autocrypt: addr=ferruh.yigit@intel.com; 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WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180422115824.105219-4-qi.z.zhang@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v7 3/5] app/testpmd: enable per queue configure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Apr 2018 17:45:53 -0000 On 4/22/2018 12:58 PM, Qi Zhang wrote: > Each queue has independent configure information in rte_port. > Base on this, we are able to add new commands to configure > different queues with different value. > > Signed-off-by: Qi Zhang <...> > @@ -1752,30 +1753,41 @@ rxtx_config_display(void) > nb_fwd_lcores, nb_fwd_ports); > > RTE_ETH_FOREACH_DEV(pid) { > - struct rte_eth_rxconf *rx_conf = &ports[pid].rx_conf; > - struct rte_eth_txconf *tx_conf = &ports[pid].tx_conf; > + struct rte_eth_rxconf *rx_conf = &ports[pid].rx_conf[0]; > + struct rte_eth_txconf *tx_conf = &ports[pid].tx_conf[0]; > > printf(" port %d:\n", (unsigned int)pid); > printf(" CRC stripping %s\n", > (ports[pid].dev_conf.rxmode.offloads & > DEV_RX_OFFLOAD_CRC_STRIP) ? > "enabled" : "disabled"); > - printf(" RX queues=%d - RX desc=%d - RX free threshold=%d\n", > - nb_rxq, nb_rxd, rx_conf->rx_free_thresh); > - printf(" RX threshold registers: pthresh=%d hthresh=%d " > - " wthresh=%d\n", > - rx_conf->rx_thresh.pthresh, > - rx_conf->rx_thresh.hthresh, > - rx_conf->rx_thresh.wthresh); > - printf(" TX queues=%d - TX desc=%d - TX free threshold=%d\n", > - nb_txq, nb_txd, tx_conf->tx_free_thresh); > - printf(" TX threshold registers: pthresh=%d hthresh=%d " > - " wthresh=%d\n", > - tx_conf->tx_thresh.pthresh, > - tx_conf->tx_thresh.hthresh, > - tx_conf->tx_thresh.wthresh); > - printf(" TX RS bit threshold=%d - TXQ offloads=0x%"PRIx64"\n", > - tx_conf->tx_rs_thresh, tx_conf->offloads); > + printf(" RX queues = %d\n", nb_rxq); > + for (qid = 0; qid < nb_rxq; qid++) { > + printf(" Queue Index = %d\n", qid); > + printf(" RX desc=%d - RX free threshold=%d\n", > + ports[pid].nb_rx_desc[qid], > + rx_conf[qid].rx_free_thresh); > + printf(" RX threshold registers: pthresh=%d hthresh=%d " > + " wthresh=%d\n", > + rx_conf[qid].rx_thresh.pthresh, > + rx_conf[qid].rx_thresh.hthresh, > + rx_conf[qid].rx_thresh.wthresh); > + } > + printf(" TX queues = %d\n", nb_txq); > + for (qid = 0; qid < nb_txq; qid++) { > + printf(" Queue Index = %d\n", qid); > + printf(" TX desc=%d - TX free threshold=%d\n", > + ports[pid].nb_tx_desc[qid], > + tx_conf[qid].tx_free_thresh); > + printf(" TX threshold registers: pthresh=%d hthresh=%d " > + " wthresh=%d\n", > + tx_conf[qid].tx_thresh.pthresh, > + tx_conf[qid].tx_thresh.hthresh, > + tx_conf[qid].tx_thresh.wthresh); > + printf(" TX RS bit threshold=%d - TXQ offloads=0x%"PRIx64"\n", > + tx_conf[qid].tx_rs_thresh, > + tx_conf[qid].offloads); > + } This part requires rebase because of recent updates, this was wrong to display queue specific values as single value, thanks for fixing.