From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D21F4404F; Wed, 12 Jun 2024 17:23:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5E02643260; Wed, 12 Jun 2024 17:06:42 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 6ECCB43251 for ; Wed, 12 Jun 2024 17:06:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204801; x=1749740801; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p5gMM5sOazpiiNYdWmZSVg9uBo23xfdXmuD1OLGyfKo=; b=VXj8Asg75b2IrtnafirJL65iRGYyfQkPFvWB7faiH0UEKPQ95AFV88r9 7JIlpbHDvNA2izJDg6fRaVC73tR6ZnyoLl1YIY5rxAWhvCJYw+oDIyu7z qcGJS6htE7sTEVNVBQIsS19jag18afv2QrwslwdTv994CT0OHTzKXsTCy Nhfpzo786sBNmNWYbITxKvhRfyBtmef43/lsdOY7WE5l2Xy94hi1AT70W GBEhV2L3xZQ7lW+2yi7Cs0dxTmwsoxZwb6lxNj94AyAQdPL9IDLsXJg4V b9KTvPymyP2KTnCmsqdgb5JNACjS44i3BquwOljV1boo3dxy9XKcslg/T A==; X-CSE-ConnectionGUID: 55pLa5E3Tm6PjnEHdQoUrA== X-CSE-MsgGUID: 2RwRk58gSki1/BeX8C7Uiw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32460033" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32460033" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:40 -0700 X-CSE-ConnectionGUID: Dv5aXPBvQJi92JsNgX/Axg== X-CSE-MsgGUID: vCZi1Xe+RJivIWfYRV58Nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925919" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:39 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: ian.stokes@intel.com, bruce.richardson@intel.com, Sergey Temerkhanov Subject: [PATCH v2 121/148] net/ice/base: allow skipping main timer programming Date: Wed, 12 Jun 2024 16:01:55 +0100 Message-ID: <8f4dc234f73c9f2f3729d98f4041170a2ba710a4.1718204529.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allow initialization functions to skip main timer programming. Signed-off-by: Sergey Temerkhanov Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 31 ++++++++++++++++++++----------- drivers/net/ice/base/ice_ptp_hw.h | 9 ++++++--- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 487eb0bd92..71a03e72dd 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5806,6 +5806,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, * ice_ptp_init_time - Initialize device time to provided value * @hw: pointer to HW struct * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) + * @wr_main_tmr: program the main timer * * Initialize the device to the specified time provided. This requires a three * step process: @@ -5815,7 +5816,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, * 3) issue an init_time timer command to synchronously switch both the source * and port timers to the new init time value at the next clock cycle. */ -int ice_ptp_init_time(struct ice_hw *hw, u64 time) +int ice_ptp_init_time(struct ice_hw *hw, u64 time, bool wr_main_tmr) { int err; u8 tmr_idx; @@ -5827,9 +5828,11 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) if (hw->phy_model == ICE_PHY_E830) return ice_ptp_write_direct_phc_time_e830(hw, time); - wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + if (wr_main_tmr) { + wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + } /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ @@ -5857,8 +5860,9 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) * ice_ptp_write_incval - Program PHC with new increment value * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * - * Program the PHC with a new increment value. This requires a three-step + * Program the timers with a new increment value. This requires a three-step * process: * * 1) Write the increment value to the source timer shadow registers @@ -5867,7 +5871,8 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) * the source and port timers to the new increment value at the next clock * cycle. */ -int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) +int ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { int err; u8 tmr_idx; @@ -5878,9 +5883,11 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) if (hw->phy_model == ICE_PHY_E830) return ice_ptp_write_direct_incval_e830(hw, incval); - /* Shadow Adjust */ - wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); - wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + if (wr_main_tmr) { + /* Shadow Adjust */ + wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); + wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + } switch (hw->phy_model) { case ICE_PHY_ETH56G: @@ -5906,17 +5913,19 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) * ice_ptp_write_incval_locked - Program new incval while holding semaphore * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * * Program a new PHC incval while holding the PTP semaphore. */ -int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) +int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { int err; if (!ice_ptp_lock(hw)) return ICE_ERR_NOT_READY; - err = ice_ptp_write_incval(hw, incval); + err = ice_ptp_write_incval(hw, incval, wr_main_tmr); ice_ptp_unlock(hw); diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index b0f0a9e6c6..eb30d5534f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -142,9 +142,12 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd); -int ice_ptp_init_time(struct ice_hw *hw, u64 time); -int ice_ptp_write_incval(struct ice_hw *hw, u64 incval); -int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); +int ice_ptp_init_time(struct ice_hw *hw, u64 time, + bool wr_main_tmr); +int ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); +int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); int ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 00d5efc45e..f4394487a8 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -6438,7 +6438,7 @@ ice_timesync_enable(struct rte_eth_dev *dev) return -1; } - ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810); + ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, true); if (ret) { PMD_DRV_LOG(ERR, "Failed to write PHC increment time value"); -- 2.43.0