From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: Scott W Taylor <scott.w.taylor@intel.com>,
bruce.richardson@intel.com, ian.stokes@intel.com
Subject: [PATCH v3 095/129] net/ice/base: merge unified E830 headers
Date: Tue, 25 Jun 2024 12:13:40 +0100 [thread overview]
Message-ID: <910d745162718679c25452ade43de50d2a7a3620.1719313663.git.anatoly.burakov@intel.com> (raw)
In-Reply-To: <cover.1719313663.git.anatoly.burakov@intel.com>
From: Scott W Taylor <scott.w.taylor@intel.com>
These changes are a result of combining E800 and E830 autogen files, as well as
multiple other infrastructural changes and E830-specific macro additions in
place of common definitions to better align with shared code.
Signed-off-by: Scott W Taylor <scott.w.taylor@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
drivers/net/ice/base/ice_common.c | 35 +-
drivers/net/ice/base/ice_hw_autogen.h | 2482 +++++++++++++++++++++----
drivers/net/ice/base/ice_nvm.c | 15 +-
3 files changed, 2158 insertions(+), 374 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 1158bc5f30..0ccff2b88c 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -801,17 +801,28 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
* Also, because we are operating on transmit timer and fc
* threshold of LFC, we don't turn on any bit in tx_tmr_priority
*/
-#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
+#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
- /* Retrieve the transmit timer */
- val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
- tx_timer_val = val &
- PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
- cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
+ if ((hw)->mac_type == ICE_MAC_E830) {
+ /* Retrieve the transmit timer */
+ val = rd32(hw, E830_PRTMAC_CL01_PAUSE_QUANTA);
+ tx_timer_val = val & E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M;
+ cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
- /* Retrieve the fc threshold */
- val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
- fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
+ /* Retrieve the fc threshold */
+ val = rd32(hw, E830_PRTMAC_CL01_QUANTA_THRESH);
+ fc_thres_val = val & E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M;
+ } else {
+ /* Retrieve the transmit timer */
+ val = rd32(hw, E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(E800_IDX_OF_LFC));
+ tx_timer_val = val &
+ E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
+ cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
+
+ /* Retrieve the fc threshold */
+ val = rd32(hw, E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(E800_IDX_OF_LFC));
+ fc_thres_val = val & E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
+ }
cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
}
@@ -2700,11 +2711,11 @@ ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
if (hw->dcf_enabled)
return;
reg_val = rd32(hw, GLQF_FD_SIZE);
- val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
+ val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw)) >>
GLQF_FD_SIZE_FD_GSIZE_S;
func_p->fd_fltr_guar =
ice_get_num_per_func(hw, val);
- val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
+ val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw)) >>
GLQF_FD_SIZE_FD_BSIZE_S;
func_p->fd_fltr_best_effort = val;
@@ -5712,7 +5723,7 @@ enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
u32 fw_mode;
/* check the current FW mode */
- fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
+ fw_mode = rd32(hw, GL_MNG_FWSM) & E800_GL_MNG_FWSM_FW_MODES_M;
if (fw_mode & ICE_FW_MODE_DBG_M)
return ICE_FW_MODE_DBG;
diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index fde5f9d86f..8c8e04e50a 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -7,11 +7,12 @@
#ifndef _ICE_HW_AUTOGEN_H_
#define _ICE_HW_AUTOGEN_H_
-#define E830_PRTTSYN_TXTIME_H(_i) (0x001E5004 + ((_i) * 64)) /* _i=0...63 */ /* Reset Source: GLOBR */
-#define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 64)) /* _i=0...63 */ /* Reset Source: GLOBR */
-#define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000 /* Reset Source: GLOBR */
-#define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020 /* Reset Source: GLOBR */
-
+#define PRTMAC_CTL_TX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE)
+#define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S)
+#define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M)
+#define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE)
+#define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S)
+#define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M)
#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
#define GL_HICR 0x00082040
@@ -35,9 +36,15 @@
#define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_S 10
#define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 10)
#define GL_RDPU_CNTRL_REQ_WB_PM_TH_S 16
-#define GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x1F, 16)
-#define GL_RDPU_CNTRL_ECO_S 21
-#define GL_RDPU_CNTRL_ECO_M MAKEMASK(0x7FF, 21)
+#define GL_RDPU_CNTRL_REQ_WB_PM_TH_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_RDPU_CNTRL_REQ_WB_PM_TH_M : E800_GL_RDPU_CNTRL_REQ_WB_PM_TH_M)
+#define E800_GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x1F, 16)
+#define E830_GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x3F, 16)
+#define GL_RDPU_CNTRL_ECO_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_RDPU_CNTRL_ECO_S : E800_GL_RDPU_CNTRL_ECO_S)
+#define E800_GL_RDPU_CNTRL_ECO_S 21
+#define E830_GL_RDPU_CNTRL_ECO_S 23
+#define GL_RDPU_CNTRL_ECO_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_RDPU_CNTRL_ECO_M : E800_GL_RDPU_CNTRL_ECO_M)
+#define E800_GL_RDPU_CNTRL_ECO_M MAKEMASK(0x7FF, 21)
+#define E830_GL_RDPU_CNTRL_ECO_M MAKEMASK(0x1FF, 23)
#define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */
#define MSIX_PBA_MAX_INDEX 2
#define MSIX_PBA_PENBIT_S 0
@@ -604,10 +611,10 @@
#define QTX_COMM_DBELL_PAGE_MAX_INDEX 16383
#define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S 0
#define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
-#define QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ) (0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */
-#define QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX 255
-#define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S 0
-#define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
+#define E800_QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ) (0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E800_QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX 255
+#define E800_QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S 0
+#define E800_QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
#define VSI_MBX_ARQBAH(_VSI) (0x02000018 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
#define VSI_MBX_ARQBAH_MAX_INDEX 767
#define VSI_MBX_ARQBAH_ARQBAH_S 0
@@ -2010,18 +2017,18 @@
#define GLTPB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
#define GLTPB_WB_RL_EN_S 16
#define GLTPB_WB_RL_EN_M BIT(16)
-#define PRTDCB_FCCFG 0x001E4640 /* Reset Source: GLOBR */
-#define PRTDCB_FCCFG_TFCE_S 3
-#define PRTDCB_FCCFG_TFCE_M MAKEMASK(0x3, 3)
-#define PRTDCB_FCRTV 0x001E4600 /* Reset Source: GLOBR */
-#define PRTDCB_FCRTV_FC_REFRESH_TH_S 0
-#define PRTDCB_FCRTV_FC_REFRESH_TH_M MAKEMASK(0xFFFF, 0)
-#define PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */
-#define PRTDCB_FCTTVN_MAX_INDEX 3
-#define PRTDCB_FCTTVN_TTV_2N_S 0
-#define PRTDCB_FCTTVN_TTV_2N_M MAKEMASK(0xFFFF, 0)
-#define PRTDCB_FCTTVN_TTV_2N_P1_S 16
-#define PRTDCB_FCTTVN_TTV_2N_P1_M MAKEMASK(0xFFFF, 16)
+#define E800_PRTDCB_FCCFG 0x001E4640 /* Reset Source: GLOBR */
+#define E800_PRTDCB_FCCFG_TFCE_S 3
+#define E800_PRTDCB_FCCFG_TFCE_M MAKEMASK(0x3, 3)
+#define E800_PRTDCB_FCRTV 0x001E4600 /* Reset Source: GLOBR */
+#define E800_PRTDCB_FCRTV_FC_REFRESH_TH_S 0
+#define E800_PRTDCB_FCRTV_FC_REFRESH_TH_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */
+#define E800_PRTDCB_FCTTVN_MAX_INDEX 3
+#define E800_PRTDCB_FCTTVN_TTV_2N_S 0
+#define E800_PRTDCB_FCTTVN_TTV_2N_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTDCB_FCTTVN_TTV_2N_P1_S 16
+#define E800_PRTDCB_FCTTVN_TTV_2N_P1_M MAKEMASK(0xFFFF, 16)
#define PRTDCB_GENC 0x00083000 /* Reset Source: CORER */
#define PRTDCB_GENC_NUMTC_S 2
#define PRTDCB_GENC_NUMTC_M MAKEMASK(0xF, 2)
@@ -2387,214 +2394,222 @@
#define TPB_WB_RL_TC_STAT_MAX_INDEX 31
#define TPB_WB_RL_TC_STAT_BUCKET_S 0
#define TPB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
-#define GL_ACLEXT_CDMD_L1SEL(_i) (0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_CDMD_L1SEL_MAX_INDEX 2
-#define GL_ACLEXT_CDMD_L1SEL_RX_SEL_S 0
-#define GL_ACLEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
-#define GL_ACLEXT_CDMD_L1SEL_TX_SEL_S 8
-#define GL_ACLEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
-#define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_S 16
-#define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
-#define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_S 24
-#define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
-#define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_S 30
-#define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
-#define GL_ACLEXT_CTLTBL_L2ADDR(_i) (0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_CTLTBL_L2ADDR_MAX_INDEX 2
-#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
-#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
-#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
-#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
-#define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_CTLTBL_L2DATA(_i) (0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_CTLTBL_L2DATA_MAX_INDEX 2
-#define GL_ACLEXT_CTLTBL_L2DATA_DATA_S 0
-#define GL_ACLEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_DFLT_L2PRFL(_i) (0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_DFLT_L2PRFL_MAX_INDEX 2
-#define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
-#define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
+#define E800_GL_ACLEXT_CDMD_L1SEL(_i) (0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_CDMD_L1SEL_MAX_INDEX 2
+#define E800_GL_ACLEXT_CDMD_L1SEL_RX_SEL_S 0
+#define E800_GL_ACLEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
+#define E800_GL_ACLEXT_CDMD_L1SEL_TX_SEL_S 8
+#define E800_GL_ACLEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
+#define E800_GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_S 16
+#define E800_GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
+#define E800_GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_S 24
+#define E800_GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
+#define E800_GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_S 30
+#define E800_GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR(_i) (0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_S 8
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_CTLTBL_L2DATA(_i) (0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_CTLTBL_L2DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_CTLTBL_L2DATA_DATA_S 0
+#define E800_GL_ACLEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_DFLT_L2PRFL(_i) (0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_DFLT_L2PRFL_MAX_INDEX 2
+#define E800_GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
+#define E800_GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
#define GL_ACLEXT_DFLT_L2PRFL_ACL(_i) (0x00393800 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_ACLEXT_DFLT_L2PRFL_ACL_MAX_INDEX 2
#define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_S 0
#define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
-#define GL_ACLEXT_FLGS_L1SEL0_1(_i) (0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_FLGS_L1SEL0_1_MAX_INDEX 2
-#define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S 0
-#define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
-#define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_S 16
-#define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
-#define GL_ACLEXT_FLGS_L1SEL2_3(_i) (0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_FLGS_L1SEL2_3_MAX_INDEX 2
-#define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S 0
-#define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
-#define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_S 16
-#define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
-#define GL_ACLEXT_FLGS_L1TBL(_i) (0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_FLGS_L1TBL_MAX_INDEX 2
-#define GL_ACLEXT_FLGS_L1TBL_LSB_S 0
-#define GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
-#define GL_ACLEXT_FLGS_L1TBL_MSB_S 16
-#define GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
-#define GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
-#define GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_FORCE_PID_MAX_INDEX 2
-#define GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
-#define GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
-#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31
-#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
-#define GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2
-#define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
-#define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_K2N_L2DATA(_i) (0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_K2N_L2DATA_MAX_INDEX 2
-#define GL_ACLEXT_K2N_L2DATA_DATA0_S 0
-#define GL_ACLEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_K2N_L2DATA_DATA1_S 8
-#define GL_ACLEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
-#define GL_ACLEXT_K2N_L2DATA_DATA2_S 16
-#define GL_ACLEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
-#define GL_ACLEXT_K2N_L2DATA_DATA3_S 24
-#define GL_ACLEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
-#define GL_ACLEXT_L2_PMASK0(_i) (0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2_PMASK0_MAX_INDEX 2
-#define GL_ACLEXT_L2_PMASK0_BITMASK_S 0
-#define GL_ACLEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_L2_PMASK1(_i) (0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2_PMASK1_MAX_INDEX 2
-#define GL_ACLEXT_L2_PMASK1_BITMASK_S 0
-#define GL_ACLEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
-#define GL_ACLEXT_L2_TMASK0(_i) (0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2_TMASK0_MAX_INDEX 2
-#define GL_ACLEXT_L2_TMASK0_BITMASK_S 0
-#define GL_ACLEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_L2_TMASK1(_i) (0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2_TMASK1_MAX_INDEX 2
-#define GL_ACLEXT_L2_TMASK1_BITMASK_S 0
-#define GL_ACLEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_L2BMP0_3(_i) (0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2BMP0_3_MAX_INDEX 2
-#define GL_ACLEXT_L2BMP0_3_BMP0_S 0
-#define GL_ACLEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_L2BMP0_3_BMP1_S 8
-#define GL_ACLEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
-#define GL_ACLEXT_L2BMP0_3_BMP2_S 16
-#define GL_ACLEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
-#define GL_ACLEXT_L2BMP0_3_BMP3_S 24
-#define GL_ACLEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
-#define GL_ACLEXT_L2BMP4_7(_i) (0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2BMP4_7_MAX_INDEX 2
-#define GL_ACLEXT_L2BMP4_7_BMP4_S 0
-#define GL_ACLEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_L2BMP4_7_BMP5_S 8
-#define GL_ACLEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
-#define GL_ACLEXT_L2BMP4_7_BMP6_S 16
-#define GL_ACLEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
-#define GL_ACLEXT_L2BMP4_7_BMP7_S 24
-#define GL_ACLEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
-#define GL_ACLEXT_L2PRTMOD(_i) (0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_L2PRTMOD_MAX_INDEX 2
-#define GL_ACLEXT_L2PRTMOD_XLT1_S 0
-#define GL_ACLEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
-#define GL_ACLEXT_L2PRTMOD_XLT2_S 8
-#define GL_ACLEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
-#define GL_ACLEXT_N2N_L2ADDR(_i) (0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_N2N_L2ADDR_MAX_INDEX 2
-#define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
-#define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_N2N_L2DATA(_i) (0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_N2N_L2DATA_MAX_INDEX 2
-#define GL_ACLEXT_N2N_L2DATA_DATA0_S 0
-#define GL_ACLEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_N2N_L2DATA_DATA1_S 8
-#define GL_ACLEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
-#define GL_ACLEXT_N2N_L2DATA_DATA2_S 16
-#define GL_ACLEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
-#define GL_ACLEXT_N2N_L2DATA_DATA3_S 24
-#define GL_ACLEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
-#define GL_ACLEXT_P2P_L1ADDR(_i) (0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_P2P_L1ADDR_MAX_INDEX 2
-#define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
-#define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_P2P_L1DATA(_i) (0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_P2P_L1DATA_MAX_INDEX 2
-#define GL_ACLEXT_P2P_L1DATA_DATA_S 0
-#define GL_ACLEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_PID_L2GKTYPE(_i) (0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_PID_L2GKTYPE_MAX_INDEX 2
-#define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
-#define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
-#define GL_ACLEXT_PLVL_SEL(_i) (0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_PLVL_SEL_MAX_INDEX 2
-#define GL_ACLEXT_PLVL_SEL_PLVL_SEL_S 0
-#define GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
-#define GL_ACLEXT_TCAM_L2ADDR(_i) (0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_TCAM_L2ADDR_MAX_INDEX 2
-#define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
-#define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_TCAM_L2DATALSB(_i) (0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_TCAM_L2DATALSB_MAX_INDEX 2
-#define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S 0
-#define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_TCAM_L2DATAMSB(_i) (0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_TCAM_L2DATAMSB_MAX_INDEX 2
-#define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S 0
-#define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_XLT0_L1ADDR(_i) (0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_XLT0_L1ADDR_MAX_INDEX 2
-#define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
-#define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_XLT0_L1DATA(_i) (0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_XLT0_L1DATA_MAX_INDEX 2
-#define GL_ACLEXT_XLT0_L1DATA_DATA_S 0
-#define GL_ACLEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_XLT1_L2ADDR(_i) (0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_XLT1_L2ADDR_MAX_INDEX 2
-#define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
-#define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_XLT1_L2DATA(_i) (0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_XLT1_L2DATA_MAX_INDEX 2
-#define GL_ACLEXT_XLT1_L2DATA_DATA_S 0
-#define GL_ACLEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_ACLEXT_XLT2_L2ADDR(_i) (0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_XLT2_L2ADDR_MAX_INDEX 2
-#define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S 0
-#define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
-#define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_S 31
-#define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
-#define GL_ACLEXT_XLT2_L2DATA(_i) (0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
-#define GL_ACLEXT_XLT2_L2DATA_MAX_INDEX 2
-#define GL_ACLEXT_XLT2_L2DATA_DATA_S 0
-#define GL_ACLEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_FLGS_L1SEL0_1(_i) (0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_FLGS_L1SEL0_1_MAX_INDEX 2
+#define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S 0
+#define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
+#define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS1_S 16
+#define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
+#define E800_GL_ACLEXT_FLGS_L1SEL2_3(_i) (0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_FLGS_L1SEL2_3_MAX_INDEX 2
+#define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S 0
+#define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
+#define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS3_S 16
+#define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
+#define E800_GL_ACLEXT_FLGS_L1TBL(_i) (0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_FLGS_L1TBL_MAX_INDEX 2
+#define E800_GL_ACLEXT_FLGS_L1TBL_LSB_S 0
+#define E800_GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
+#define E800_GL_ACLEXT_FLGS_L1TBL_MSB_S 16
+#define E800_GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
+#define E800_GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2
+#define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
+#define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
+#define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
+#define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define E800_GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_FORCE_PID_MAX_INDEX 2
+#define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
+#define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
+#define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31
+#define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
+#define E800_GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
+#define E800_GL_ACLEXT_K2N_L2ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_K2N_L2DATA(_i) (0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_K2N_L2DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA0_S 0
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA1_S 8
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA2_S 16
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA3_S 24
+#define E800_GL_ACLEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
+#define E800_GL_ACLEXT_L2_PMASK0(_i) (0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2_PMASK0_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2_PMASK0_BITMASK_S 0
+#define E800_GL_ACLEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_L2_PMASK1(_i) (0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2_PMASK1_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2_PMASK1_BITMASK_S 0
+#define E800_GL_ACLEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
+#define E800_GL_ACLEXT_L2_TMASK0(_i) (0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2_TMASK0_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2_TMASK0_BITMASK_S 0
+#define E800_GL_ACLEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_L2_TMASK1(_i) (0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2_TMASK1_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2_TMASK1_BITMASK_S 0
+#define E800_GL_ACLEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_L2BMP0_3(_i) (0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2BMP0_3_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2BMP0_3_BMP0_S 0
+#define E800_GL_ACLEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_L2BMP0_3_BMP1_S 8
+#define E800_GL_ACLEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
+#define E800_GL_ACLEXT_L2BMP0_3_BMP2_S 16
+#define E800_GL_ACLEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
+#define E800_GL_ACLEXT_L2BMP0_3_BMP3_S 24
+#define E800_GL_ACLEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
+#define E800_GL_ACLEXT_L2BMP4_7(_i) (0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2BMP4_7_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2BMP4_7_BMP4_S 0
+#define E800_GL_ACLEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_L2BMP4_7_BMP5_S 8
+#define E800_GL_ACLEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
+#define E800_GL_ACLEXT_L2BMP4_7_BMP6_S 16
+#define E800_GL_ACLEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
+#define E800_GL_ACLEXT_L2BMP4_7_BMP7_S 24
+#define E800_GL_ACLEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
+#define E800_GL_ACLEXT_L2PRTMOD(_i) (0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_L2PRTMOD_MAX_INDEX 2
+#define E800_GL_ACLEXT_L2PRTMOD_XLT1_S 0
+#define E800_GL_ACLEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
+#define E800_GL_ACLEXT_L2PRTMOD_XLT2_S 8
+#define E800_GL_ACLEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
+#define E800_GL_ACLEXT_N2N_L2ADDR(_i) (0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_N2N_L2ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
+#define E800_GL_ACLEXT_N2N_L2ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_N2N_L2DATA(_i) (0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_N2N_L2DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA0_S 0
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA1_S 8
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA2_S 16
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA3_S 24
+#define E800_GL_ACLEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
+#define E800_GL_ACLEXT_P2P_L1ADDR(_i) (0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_P2P_L1ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
+#define E800_GL_ACLEXT_P2P_L1ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_P2P_L1DATA(_i) (0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_P2P_L1DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_P2P_L1DATA_DATA_S 0
+#define E800_GL_ACLEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_PID_L2GKTYPE(_i) (0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_PID_L2GKTYPE_MAX_INDEX 2
+#define E800_GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
+#define E800_GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
+#define E800_GL_ACLEXT_PLVL_SEL(_i) (0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_PLVL_SEL_MAX_INDEX 2
+#define E800_GL_ACLEXT_PLVL_SEL_PLVL_SEL_S 0
+#define E800_GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
+#define E800_GL_ACLEXT_TCAM_L2ADDR(_i) (0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_TCAM_L2ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
+#define E800_GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_TCAM_L2DATALSB(_i) (0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_TCAM_L2DATALSB_MAX_INDEX 2
+#define E800_GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S 0
+#define E800_GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_TCAM_L2DATAMSB(_i) (0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_TCAM_L2DATAMSB_MAX_INDEX 2
+#define E800_GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S 0
+#define E800_GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_XLT0_L1ADDR(_i) (0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_XLT0_L1ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
+#define E800_GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_XLT0_L1DATA(_i) (0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_XLT0_L1DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_XLT0_L1DATA_DATA_S 0
+#define E800_GL_ACLEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_XLT1_L2ADDR(_i) (0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_XLT1_L2ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
+#define E800_GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_XLT1_L2DATA(_i) (0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_XLT1_L2DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_XLT1_L2DATA_DATA_S 0
+#define E800_GL_ACLEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GL_ACLEXT_XLT2_L2ADDR(_i) (0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_XLT2_L2ADDR_MAX_INDEX 2
+#define E800_GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S 0
+#define E800_GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
+#define E800_GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_S 31
+#define E800_GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M BIT(31)
+#define E800_GL_ACLEXT_XLT2_L2DATA(_i) (0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
+#define E800_GL_ACLEXT_XLT2_L2DATA_MAX_INDEX 2
+#define E800_GL_ACLEXT_XLT2_L2DATA_DATA_S 0
+#define E800_GL_ACLEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
#define GL_PREEXT_CDMD_L1SEL(_i) (0x0020F054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PREEXT_CDMD_L1SEL_MAX_INDEX 2
#define GL_PREEXT_CDMD_L1SEL_RX_SEL_S 0
-#define GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
+#define GL_PREEXT_CDMD_L1SEL_RX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_RX_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_RX_SEL_M)
+#define E800_GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
+#define E830_GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x3F, 0)
#define GL_PREEXT_CDMD_L1SEL_TX_SEL_S 8
-#define GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
+#define GL_PREEXT_CDMD_L1SEL_TX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_TX_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_TX_SEL_M)
+#define E800_GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
+#define E830_GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x3F, 8)
#define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_S 16
-#define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
+#define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M)
+#define E800_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
+#define E830_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x3F, 16)
#define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_S 24
-#define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
+#define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M : E800_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M)
+#define E800_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
+#define E830_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x3F, 24)
#define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_S 30
#define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
#define GL_PREEXT_CTLTBL_L2ADDR(_i) (0x0020F084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
@@ -2616,15 +2631,23 @@
#define GL_PREEXT_FLGS_L1SEL0_1(_i) (0x0020F06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PREEXT_FLGS_L1SEL0_1_MAX_INDEX 2
#define GL_PREEXT_FLGS_L1SEL0_1_FLS0_S 0
-#define GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
+#define GL_PREEXT_FLGS_L1SEL0_1_FLS0_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M : E800_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M)
+#define E800_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
+#define E830_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x3FF, 0)
#define GL_PREEXT_FLGS_L1SEL0_1_FLS1_S 16
-#define GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
+#define GL_PREEXT_FLGS_L1SEL0_1_FLS1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M : E800_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M)
+#define E800_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
+#define E830_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x3FF, 16)
#define GL_PREEXT_FLGS_L1SEL2_3(_i) (0x0020F078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PREEXT_FLGS_L1SEL2_3_MAX_INDEX 2
#define GL_PREEXT_FLGS_L1SEL2_3_FLS2_S 0
-#define GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
+#define GL_PREEXT_FLGS_L1SEL2_3_FLS2_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M : E800_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M)
+#define E800_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
+#define E830_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x3FF, 0)
#define GL_PREEXT_FLGS_L1SEL2_3_FLS3_S 16
-#define GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
+#define GL_PREEXT_FLGS_L1SEL2_3_FLS3_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M : E800_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M)
+#define E800_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
+#define E830_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x3FF, 16)
#define GL_PREEXT_FLGS_L1TBL(_i) (0x0020F060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PREEXT_FLGS_L1TBL_MAX_INDEX 2
#define GL_PREEXT_FLGS_L1TBL_LSB_S 0
@@ -2782,13 +2805,21 @@
#define GL_PSTEXT_CDMD_L1SEL(_i) (0x0020E054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PSTEXT_CDMD_L1SEL_MAX_INDEX 2
#define GL_PSTEXT_CDMD_L1SEL_RX_SEL_S 0
-#define GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
+#define GL_PSTEXT_CDMD_L1SEL_RX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M)
+#define E800_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
+#define E830_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x3F, 0)
#define GL_PSTEXT_CDMD_L1SEL_TX_SEL_S 8
-#define GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
+#define GL_PSTEXT_CDMD_L1SEL_TX_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M)
+#define E800_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
+#define E830_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x3F, 8)
#define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_S 16
-#define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
+#define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M)
+#define E800_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
+#define E830_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x3F, 16)
#define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_S 24
-#define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
+#define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M : E800_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M)
+#define E800_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
+#define E830_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x3F, 24)
#define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_S 30
#define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
#define GL_PSTEXT_CTLTBL_L2ADDR(_i) (0x0020E084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
@@ -2818,15 +2849,23 @@
#define GL_PSTEXT_FLGS_L1SEL0_1(_i) (0x0020E06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PSTEXT_FLGS_L1SEL0_1_MAX_INDEX 2
#define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_S 0
-#define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
+#define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M : E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M)
+#define E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
+#define E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x3FF, 0)
#define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_S 16
-#define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
+#define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M : E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M)
+#define E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
+#define E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x3FF, 16)
#define GL_PSTEXT_FLGS_L1SEL2_3(_i) (0x0020E078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PSTEXT_FLGS_L1SEL2_3_MAX_INDEX 2
#define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_S 0
-#define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
+#define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M : E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M)
+#define E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
+#define E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x3FF, 0)
#define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_S 16
-#define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
+#define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M : E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M)
+#define E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
+#define E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x3FF, 16)
#define GL_PSTEXT_FLGS_L1TBL(_i) (0x0020E060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
#define GL_PSTEXT_FLGS_L1TBL_MAX_INDEX 2
#define GL_PSTEXT_FLGS_L1TBL_LSB_S 0
@@ -4468,8 +4507,8 @@
#define GL_UFUSE_SOC_SOC_TYPE_M BIT(10)
#define GL_UFUSE_SOC_BTS_MODE_S 11
#define GL_UFUSE_SOC_BTS_MODE_M BIT(11)
-#define GL_UFUSE_SOC_SPARE_FUSES_S 12
-#define GL_UFUSE_SOC_SPARE_FUSES_M MAKEMASK(0xF, 12)
+#define E800_GL_UFUSE_SOC_SPARE_FUSES_S 12
+#define E800_GL_UFUSE_SOC_SPARE_FUSES_M MAKEMASK(0xF, 12)
#define EMPINT_GPIO_ENA 0x000880C0 /* Reset Source: POR */
#define EMPINT_GPIO_ENA_GPIO0_ENA_S 0
#define EMPINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
@@ -5226,76 +5265,96 @@
#define VSILAN_QTABLE_QINDEX_0_M MAKEMASK(0x7FF, 0)
#define VSILAN_QTABLE_QINDEX_1_S 16
#define VSILAN_QTABLE_QINDEX_1_M MAKEMASK(0x7FF, 16)
-#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E31C0 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0
-#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)
-#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E34C0 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0
-#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
-#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0
-#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
-#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
-#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0
-#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0
-#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E32A0 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0
-#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_HSEC_CTL_RX_QUANTA_S 0x001E3C40 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0
-#define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E31A0 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0
-#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
-#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
-#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0
-#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E3960 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0
-#define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
-#define PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E3980 /* Reset Source: GLOBR */
-#define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0
-#define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_LINK_DOWN_COUNTER 0x001E47C0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E31C0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E34C0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
+#define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E32A0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_RX_QUANTA_S 0x001E3C40 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0
+#define E800_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E31A0 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
+#define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E3960 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0
+#define E800_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E3980 /* Reset Source: GLOBR */
+#define E800_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0
+#define E800_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0)
+#define PRTMAC_LINK_DOWN_COUNTER_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_LINK_DOWN_COUNTER : E800_PRTMAC_LINK_DOWN_COUNTER)
+#define E800_PRTMAC_LINK_DOWN_COUNTER 0x001E47C0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_LINK_DOWN_COUNTER 0x001E2460 /* Reset Source: GLOBR */
#define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_S 0
#define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
-#define PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 7
+#define PRTMAC_MD_OVRRIDE_ENABLE_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_ENABLE(_i) : E800_PRTMAC_MD_OVRRIDE_ENABLE(_i))
+#define E800_PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
+#define E830_PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E2500 + ((_i) * 32)) /* _i=0...1 */ /* Reset Source: GLOBR */
+#define PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX : E800_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX)
+#define E800_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 7
+#define E830_PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX 1
#define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_S 0
#define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
-#define PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
-#define PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 7
+#define PRTMAC_MD_OVRRIDE_VAL_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_VAL(_i) : E800_PRTMAC_MD_OVRRIDE_VAL(_i))
+#define E800_PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
+#define E830_PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E2600 + ((_i) * 32)) /* _i=0...1 */ /* Reset Source: GLOBR */
+#define PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX : E800_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX)
+#define E800_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 7
+#define E830_PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX 1
#define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_S 0
#define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
#define PRTMAC_RX_CNT_MRKR 0x001E48E0 /* Reset Source: GLOBR */
#define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_S 0
#define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_RX_PKT_DRP_CNT 0x001E3C20 /* Reset Source: GLOBR */
+#define PRTMAC_RX_PKT_DRP_CNT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT : E800_PRTMAC_RX_PKT_DRP_CNT)
+#define E800_PRTMAC_RX_PKT_DRP_CNT 0x001E3C20 /* Reset Source: GLOBR */
+#define E830_PRTMAC_RX_PKT_DRP_CNT 0x001E2420 /* Reset Source: GLOBR */
#define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_S 0
-#define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 16
-#define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16)
+#define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M : E800_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M)
+#define E800_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFF, 0)
+#define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S : E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S)
+#define E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 16
+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 28
+#define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M : E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M)
+#define E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xF, 28)
#define PRTMAC_TX_CNT_MRKR 0x001E48C0 /* Reset Source: GLOBR */
#define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_S 0
#define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
-#define PRTMAC_TX_LNK_UP_CNT 0x001E4840 /* Reset Source: GLOBR */
+#define PRTMAC_TX_LNK_UP_CNT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_TX_LNK_UP_CNT : E800_PRTMAC_TX_LNK_UP_CNT)
+#define E800_PRTMAC_TX_LNK_UP_CNT 0x001E4840 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TX_LNK_UP_CNT 0x001E2480 /* Reset Source: GLOBR */
#define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_S 0
#define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_M MAKEMASK(0xFFFF, 0)
#define GL_MDCK_CFG1_TX_PQM 0x002D2DF4 /* Reset Source: CORER */
@@ -5356,8 +5415,8 @@
#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24)
#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25
#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)
-#define GL_MDCK_EN_TX_PQM_RSVD_S 26
-#define GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)
+#define E800_GL_MDCK_EN_TX_PQM_RSVD_S 26
+#define E800_GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)
#define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
#define GL_MDCK_RX_DESC_ADDR_S 0
#define GL_MDCK_RX_DESC_ADDR_M BIT(0)
@@ -5476,9 +5535,15 @@
#define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */
#define GL_MNG_FWSM_FW_LOADING_M BIT(30)
#define GL_MNG_FWSM_FW_MODES_S 0
-#define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0)
-#define GL_MNG_FWSM_RSV0_S 3
-#define GL_MNG_FWSM_RSV0_M MAKEMASK(0x7F, 3)
+#define GL_MNG_FWSM_FW_MODES_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FWSM_FW_MODES_M : E800_GL_MNG_FWSM_FW_MODES_M)
+#define E800_GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0)
+#define E830_GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x3, 0)
+#define GL_MNG_FWSM_RSV0_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FWSM_RSV0_S : E800_GL_MNG_FWSM_RSV0_S)
+#define E800_GL_MNG_FWSM_RSV0_S 3
+#define E830_GL_MNG_FWSM_RSV0_S 2
+#define GL_MNG_FWSM_RSV0_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FWSM_RSV0_M : E800_GL_MNG_FWSM_RSV0_M)
+#define E800_GL_MNG_FWSM_RSV0_M MAKEMASK(0x7F, 3)
+#define E830_GL_MNG_FWSM_RSV0_M MAKEMASK(0xFF, 2)
#define GL_MNG_FWSM_EEP_RELOAD_IND_S 10
#define GL_MNG_FWSM_EEP_RELOAD_IND_M BIT(10)
#define GL_MNG_FWSM_RSV1_S 11
@@ -5502,12 +5567,20 @@
#define GL_MNG_HWARB_CTRL 0x000B6130 /* Reset Source: POR */
#define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_S 0
#define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M BIT(0)
-#define GL_MNG_SHA_EXTEND(_i) (0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
-#define GL_MNG_SHA_EXTEND_MAX_INDEX 7
+#define GL_MNG_SHA_EXTEND_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND(_i) : E800_GL_MNG_SHA_EXTEND(_i))
+#define E800_GL_MNG_SHA_EXTEND(_i) (0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
+#define E830_GL_MNG_SHA_EXTEND(_i) (0x00083340 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
+#define GL_MNG_SHA_EXTEND_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND_MAX_INDEX : E800_GL_MNG_SHA_EXTEND_MAX_INDEX)
+#define E800_GL_MNG_SHA_EXTEND_MAX_INDEX 7
+#define E830_GL_MNG_SHA_EXTEND_MAX_INDEX 11
#define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_S 0
#define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_M MAKEMASK(0xFFFFFFFF, 0)
-#define GL_MNG_SHA_EXTEND_ROM(_i) (0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
-#define GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 7
+#define GL_MNG_SHA_EXTEND_ROM_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND_ROM(_i) : E800_GL_MNG_SHA_EXTEND_ROM(_i))
+#define E800_GL_MNG_SHA_EXTEND_ROM(_i) (0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
+#define E830_GL_MNG_SHA_EXTEND_ROM(_i) (0x000832C0 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
+#define GL_MNG_SHA_EXTEND_ROM_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX : E800_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX)
+#define E800_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 7
+#define E830_GL_MNG_SHA_EXTEND_ROM_MAX_INDEX 11
#define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_S 0
#define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_M MAKEMASK(0xFFFFFFFF, 0)
#define GL_MNG_SHA_EXTEND_STATUS 0x00083148 /* Reset Source: EMPR */
@@ -5906,8 +5979,8 @@
#define GLPCI_CAPSUP 0x0009DE8C /* Reset Source: PCIR */
#define GLPCI_CAPSUP_PCIE_VER_S 0
#define GLPCI_CAPSUP_PCIE_VER_M BIT(0)
-#define GLPCI_CAPSUP_RESERVED_2_S 1
-#define GLPCI_CAPSUP_RESERVED_2_M BIT(1)
+#define E800_GLPCI_CAPSUP_RESERVED_2_S 1
+#define E800_GLPCI_CAPSUP_RESERVED_2_M BIT(1)
#define GLPCI_CAPSUP_LTR_EN_S 2
#define GLPCI_CAPSUP_LTR_EN_M BIT(2)
#define GLPCI_CAPSUP_TPH_EN_S 3
@@ -6357,9 +6430,9 @@
#define PFPE_MRTEIDXMASK 0x0050A300 /* Reset Source: PFR */
#define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
#define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
-#define PFPE_RCVUNEXPECTEDERROR 0x0050A380 /* Reset Source: PFR */
-#define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
-#define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
+#define E800_PFPE_RCVUNEXPECTEDERROR 0x0050A380 /* Reset Source: PFR */
+#define E800_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
+#define E800_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
#define PFPE_TCPNOWTIMER 0x0050A280 /* Reset Source: PFR */
#define PFPE_TCPNOWTIMER_TCP_NOW_S 0
#define PFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
@@ -6428,10 +6501,10 @@
#define VFPE_IPCONFIG0_USEENTIREIDRANGE_M BIT(16)
#define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17
#define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M BIT(17)
-#define VFPE_RCVUNEXPECTEDERROR(_VF) (0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
-#define VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 255
-#define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
-#define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
+#define E800_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
+#define E800_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 255
+#define E800_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
+#define E800_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
#define VFPE_TCPNOWTIMER(_VF) (0x00509400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
#define VFPE_TCPNOWTIMER_MAX_INDEX 255
#define VFPE_TCPNOWTIMER_TCP_NOW_S 0
@@ -7135,15 +7208,21 @@
#define GLRPB_DHW(_i) (0x000AC000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
#define GLRPB_DHW_MAX_INDEX 15
#define GLRPB_DHW_DHW_TCN_S 0
-#define GLRPB_DHW_DHW_TCN_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_DHW_DHW_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_DHW_DHW_TCN_M : E800_GLRPB_DHW_DHW_TCN_M)
+#define E800_GLRPB_DHW_DHW_TCN_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_DHW_DHW_TCN_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_DLW(_i) (0x000AC044 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
#define GLRPB_DLW_MAX_INDEX 15
#define GLRPB_DLW_DLW_TCN_S 0
-#define GLRPB_DLW_DLW_TCN_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_DLW_DLW_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_DLW_DLW_TCN_M : E800_GLRPB_DLW_DLW_TCN_M)
+#define E800_GLRPB_DLW_DLW_TCN_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_DLW_DLW_TCN_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_DPS(_i) (0x000AC084 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
#define GLRPB_DPS_MAX_INDEX 15
#define GLRPB_DPS_DPS_TCN_S 0
-#define GLRPB_DPS_DPS_TCN_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_DPS_DPS_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_DPS_DPS_TCN_M : E800_GLRPB_DPS_DPS_TCN_M)
+#define E800_GLRPB_DPS_DPS_TCN_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_DPS_DPS_TCN_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_DSI_EN 0x000AC324 /* Reset Source: CORER */
#define GLRPB_DSI_EN_DSI_EN_S 0
#define GLRPB_DSI_EN_DSI_EN_M BIT(0)
@@ -7152,15 +7231,21 @@
#define GLRPB_SHW(_i) (0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLRPB_SHW_MAX_INDEX 7
#define GLRPB_SHW_SHW_S 0
-#define GLRPB_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_SHW_SHW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_SHW_SHW_M : E800_GLRPB_SHW_SHW_M)
+#define E800_GLRPB_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_SHW_SHW_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_SLW(_i) (0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLRPB_SLW_MAX_INDEX 7
#define GLRPB_SLW_SLW_S 0
-#define GLRPB_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_SLW_SLW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_SLW_SLW_M : E800_GLRPB_SLW_SLW_M)
+#define E800_GLRPB_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_SLW_SLW_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_SPS(_i) (0x000AC0C4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLRPB_SPS_MAX_INDEX 7
#define GLRPB_SPS_SPS_TCN_S 0
-#define GLRPB_SPS_SPS_TCN_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_SPS_SPS_TCN_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_SPS_SPS_TCN_M : E800_GLRPB_SPS_SPS_TCN_M)
+#define E800_GLRPB_SPS_SPS_TCN_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_SPS_SPS_TCN_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_TC_CFG(_i) (0x000AC2A4 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLRPB_TC_CFG_MAX_INDEX 31
#define GLRPB_TC_CFG_D_POOL_S 0
@@ -7170,11 +7255,15 @@
#define GLRPB_TCHW(_i) (0x000AC330 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLRPB_TCHW_MAX_INDEX 31
#define GLRPB_TCHW_TCHW_S 0
-#define GLRPB_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_TCHW_TCHW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_TCHW_TCHW_M : E800_GLRPB_TCHW_TCHW_M)
+#define E800_GLRPB_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_TCHW_TCHW_M MAKEMASK(0x3FFFFF, 0)
#define GLRPB_TCLW(_i) (0x000AC3B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
#define GLRPB_TCLW_MAX_INDEX 31
#define GLRPB_TCLW_TCLW_S 0
-#define GLRPB_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
+#define GLRPB_TCLW_TCLW_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLRPB_TCLW_TCLW_M : E800_GLRPB_TCLW_TCLW_M)
+#define E800_GLRPB_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRPB_TCLW_TCLW_M MAKEMASK(0x3FFFFF, 0)
#define GLQF_APBVT(_i) (0x00450000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
#define GLQF_APBVT_MAX_INDEX 2047
#define GLQF_APBVT_APBVT_S 0
@@ -7187,9 +7276,13 @@
#define GLQF_FD_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
#define GLQF_FD_CNT 0x00460018 /* Reset Source: CORER */
#define GLQF_FD_CNT_FD_GCNT_S 0
-#define GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
+#define GLQF_FD_CNT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_CNT_FD_GCNT_M : E800_GLQF_FD_CNT_FD_GCNT_M)
+#define E800_GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
+#define E830_GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
#define GLQF_FD_CNT_FD_BCNT_S 16
-#define GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
+#define GLQF_FD_CNT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_CNT_FD_BCNT_M : E800_GLQF_FD_CNT_FD_BCNT_M)
+#define E800_GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
+#define E830_GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
#define GLQF_FD_CTL 0x00460000 /* Reset Source: CORER */
#define GLQF_FD_CTL_FDLONG_S 0
#define GLQF_FD_CTL_FDLONG_M MAKEMASK(0xF, 0)
@@ -7199,12 +7292,18 @@
#define GLQF_FD_CTL_FLT_ADDR_REPORT_M BIT(5)
#define GLQF_FD_SIZE 0x00460010 /* Reset Source: CORER */
#define GLQF_FD_SIZE_FD_GSIZE_S 0
-#define GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
+#define GLQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_SIZE_FD_GSIZE_M : E800_GLQF_FD_SIZE_FD_GSIZE_M)
+#define E800_GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
+#define E830_GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0)
#define GLQF_FD_SIZE_FD_BSIZE_S 16
-#define GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
+#define GLQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FD_SIZE_FD_BSIZE_M : E800_GLQF_FD_SIZE_FD_BSIZE_M)
+#define E800_GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
+#define E830_GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16)
#define GLQF_FDCNT_0 0x00460020 /* Reset Source: CORER */
#define GLQF_FDCNT_0_BUCKETCNT_S 0
-#define GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0x7FFF, 0)
+#define GLQF_FDCNT_0_BUCKETCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLQF_FDCNT_0_BUCKETCNT_M : E800_GLQF_FDCNT_0_BUCKETCNT_M)
+#define E800_GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0x7FFF, 0)
+#define E830_GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0xFFFF, 0)
#define GLQF_FDCNT_0_CNT_NOT_VLD_S 31
#define GLQF_FDCNT_0_CNT_NOT_VLD_M BIT(31)
#define GLQF_FDEVICTENA(_i) (0x00452000 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
@@ -7428,22 +7527,34 @@
#define GLQF_PROF2TC_REGION_7_M MAKEMASK(0x7, 29)
#define PFQF_FD_CNT 0x00460180 /* Reset Source: CORER */
#define PFQF_FD_CNT_FD_GCNT_S 0
-#define PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
+#define PFQF_FD_CNT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_CNT_FD_GCNT_M : E800_PFQF_FD_CNT_FD_GCNT_M)
+#define E800_PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
+#define E830_PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
#define PFQF_FD_CNT_FD_BCNT_S 16
-#define PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
+#define PFQF_FD_CNT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_CNT_FD_BCNT_M : E800_PFQF_FD_CNT_FD_BCNT_M)
+#define E800_PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
+#define E830_PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
#define PFQF_FD_ENA 0x0043A000 /* Reset Source: CORER */
#define PFQF_FD_ENA_FD_ENA_S 0
#define PFQF_FD_ENA_FD_ENA_M BIT(0)
#define PFQF_FD_SIZE 0x00460100 /* Reset Source: CORER */
#define PFQF_FD_SIZE_FD_GSIZE_S 0
-#define PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
+#define PFQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SIZE_FD_GSIZE_M : E800_PFQF_FD_SIZE_FD_GSIZE_M)
+#define E800_PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
+#define E830_PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0)
#define PFQF_FD_SIZE_FD_BSIZE_S 16
-#define PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
+#define PFQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SIZE_FD_BSIZE_M : E800_PFQF_FD_SIZE_FD_BSIZE_M)
+#define E800_PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
+#define E830_PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16)
#define PFQF_FD_SUBTRACT 0x00460200 /* Reset Source: CORER */
#define PFQF_FD_SUBTRACT_FD_GCNT_S 0
-#define PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
+#define PFQF_FD_SUBTRACT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SUBTRACT_FD_GCNT_M : E800_PFQF_FD_SUBTRACT_FD_GCNT_M)
+#define E800_PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
+#define E830_PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
#define PFQF_FD_SUBTRACT_FD_BCNT_S 16
-#define PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
+#define PFQF_FD_SUBTRACT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFQF_FD_SUBTRACT_FD_BCNT_M : E800_PFQF_FD_SUBTRACT_FD_BCNT_M)
+#define E800_PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
+#define E830_PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
#define PFQF_HLUT(_i) (0x00430000 + ((_i) * 64)) /* _i=0...511 */ /* Reset Source: CORER */
#define PFQF_HLUT_MAX_INDEX 511
#define PFQF_HLUT_LUT0_S 0
@@ -7671,20 +7782,20 @@
#define GLPRT_AORCL_AORCL_M MAKEMASK(0xFFFFFFFF, 0)
#define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLPRT_BPRCH_MAX_INDEX 7
-#define GLPRT_BPRCH_UPRCH_S 0
-#define GLPRT_BPRCH_UPRCH_M MAKEMASK(0xFF, 0)
+#define E800_GLPRT_BPRCH_UPRCH_S 0
+#define E800_GLPRT_BPRCH_UPRCH_M MAKEMASK(0xFF, 0)
#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLPRT_BPRCL_MAX_INDEX 7
-#define GLPRT_BPRCL_UPRCH_S 0
-#define GLPRT_BPRCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GLPRT_BPRCL_UPRCH_S 0
+#define E800_GLPRT_BPRCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLPRT_BPTCH_MAX_INDEX 7
-#define GLPRT_BPTCH_UPRCH_S 0
-#define GLPRT_BPTCH_UPRCH_M MAKEMASK(0xFF, 0)
+#define E800_GLPRT_BPTCH_UPRCH_S 0
+#define E800_GLPRT_BPTCH_UPRCH_M MAKEMASK(0xFF, 0)
#define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLPRT_BPTCL_MAX_INDEX 7
-#define GLPRT_BPTCL_UPRCH_S 0
-#define GLPRT_BPTCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GLPRT_BPTCL_UPRCH_S 0
+#define E800_GLPRT_BPTCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLPRT_CRCERRS_MAX_INDEX 7
#define GLPRT_CRCERRS_CRCERRS_S 0
@@ -7999,8 +8110,8 @@
#define GLPRT_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
#define GLPRT_UPTCL_MAX_INDEX 7
-#define GLPRT_UPTCL_VUPTCH_S 0
-#define GLPRT_UPTCL_VUPTCH_M MAKEMASK(0xFFFFFFFF, 0)
+#define E800_GLPRT_UPTCL_VUPTCH_S 0
+#define E800_GLPRT_UPTCL_VUPTCH_M MAKEMASK(0xFFFFFFFF, 0)
#define GLSTAT_ACL_CNT_0_H(_i) (0x00388004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
#define GLSTAT_ACL_CNT_0_H_MAX_INDEX 511
#define GLSTAT_ACL_CNT_0_H_CNT_MSB_S 0
@@ -8895,9 +9006,13 @@
#define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
#define VSIQF_FD_CNT_MAX_INDEX 767
#define VSIQF_FD_CNT_FD_GCNT_S 0
-#define VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0x3FFF, 0)
+#define VSIQF_FD_CNT_FD_GCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_CNT_FD_GCNT_M : E800_VSIQF_FD_CNT_FD_GCNT_M)
+#define E800_VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0x3FFF, 0)
+#define E830_VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
#define VSIQF_FD_CNT_FD_BCNT_S 16
-#define VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0x3FFF, 16)
+#define VSIQF_FD_CNT_FD_BCNT_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_CNT_FD_BCNT_M : E800_VSIQF_FD_CNT_FD_BCNT_M)
+#define E800_VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0x3FFF, 16)
+#define E830_VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
#define VSIQF_FD_CTL1(_VSI) (0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
#define VSIQF_FD_CTL1_MAX_INDEX 767
#define VSIQF_FD_CTL1_FLT_ENA_S 0
@@ -8921,9 +9036,13 @@
#define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
#define VSIQF_FD_SIZE_MAX_INDEX 767
#define VSIQF_FD_SIZE_FD_GSIZE_S 0
-#define VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x3FFF, 0)
+#define VSIQF_FD_SIZE_FD_GSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_SIZE_FD_GSIZE_M : E800_VSIQF_FD_SIZE_FD_GSIZE_M)
+#define E800_VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x3FFF, 0)
+#define E830_VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0)
#define VSIQF_FD_SIZE_FD_BSIZE_S 16
-#define VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x3FFF, 16)
+#define VSIQF_FD_SIZE_FD_BSIZE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VSIQF_FD_SIZE_FD_BSIZE_M : E800_VSIQF_FD_SIZE_FD_BSIZE_M)
+#define E800_VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x3FFF, 16)
+#define E830_VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16)
#define VSIQF_HASH_CTL(_VSI) (0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
#define VSIQF_HASH_CTL_MAX_INDEX 767
#define VSIQF_HASH_CTL_HASH_LUT_SEL_S 0
@@ -9047,7 +9166,9 @@
#define PFPM_WUS_FLX7_M BIT(23)
#define PFPM_WUS_FW_RST_WK_S 31
#define PFPM_WUS_FW_RST_WK_M BIT(31)
-#define PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
+#define PRTPM_SAH_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTPM_SAH(_i) : E800_PRTPM_SAH(_i))
+#define E800_PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
+#define E830_PRTPM_SAH(_i) (0x001E2380 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
#define PRTPM_SAH_MAX_INDEX 3
#define PRTPM_SAH_PFPM_SAH_S 0
#define PRTPM_SAH_PFPM_SAH_M MAKEMASK(0xFFFF, 0)
@@ -9057,7 +9178,9 @@
#define PRTPM_SAH_MC_MAG_EN_M BIT(30)
#define PRTPM_SAH_AV_S 31
#define PRTPM_SAH_AV_M BIT(31)
-#define PRTPM_SAL(_i) (0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
+#define PRTPM_SAL_BY_MAC(hw, _i) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTPM_SAL(_i) : E800_PRTPM_SAL(_i))
+#define E800_PRTPM_SAL(_i) (0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
+#define E830_PRTPM_SAL(_i) (0x001E2300 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
#define PRTPM_SAL_MAX_INDEX 3
#define PRTPM_SAL_PFPM_SAL_S 0
#define PRTPM_SAL_PFPM_SAL_M MAKEMASK(0xFFFFFFFF, 0)
@@ -9070,7 +9193,9 @@
#define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_M MAKEMASK(0x3, 13)
#define GLPE_CQM_FUNC_INVALIDATE_ENABLE_S 31
#define GLPE_CQM_FUNC_INVALIDATE_ENABLE_M BIT(31)
-#define VFPE_MRTEIDXMASK 0x00009000 /* Reset Source: PFR */
+#define VFPE_MRTEIDXMASK_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VFPE_MRTEIDXMASK : E800_VFPE_MRTEIDXMASK)
+#define E800_VFPE_MRTEIDXMASK 0x00009000 /* Reset Source: PFR */
+#define E830_VFPE_MRTEIDXMASK(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
#define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
#define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
#define GLTSYN_HH_DLAY 0x0008881C /* Reset Source: CORER */
@@ -9173,8 +9298,12 @@
#define VFINT_ITR0_MAX_INDEX 2
#define VFINT_ITR0_INTERVAL_S 0
#define VFINT_ITR0_INTERVAL_M MAKEMASK(0xFFF, 0)
-#define VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */
-#define VFINT_ITRN_MAX_INDEX 2
+#define VFINT_ITRN_BY_MAC(hw, _i, _j) ((hw)->mac_type == ICE_MAC_E830 ? E830_VFINT_ITRN(_i, _j) : E800_VFINT_ITRN(_i, _j))
+#define E800_VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */
+#define E830_VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...2 */ /* Reset Source: CORER */
+#define VFINT_ITRN_MAX_INDEX_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_VFINT_ITRN_MAX_INDEX : E800_VFINT_ITRN_MAX_INDEX)
+#define E800_VFINT_ITRN_MAX_INDEX 2
+#define E830_VFINT_ITRN_MAX_INDEX 15
#define VFINT_ITRN_INTERVAL_S 0
#define VFINT_ITRN_INTERVAL_M MAKEMASK(0xFFF, 0)
#define QRX_TAIL1(_QRX) (0x00002000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
@@ -9469,13 +9598,13 @@
#define VFPE_IPCONFIG01_USEENTIREIDRANGE_M BIT(16)
#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S 17
#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M BIT(17)
-#define VFPE_MRTEIDXMASK1(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
-#define VFPE_MRTEIDXMASK1_MAX_INDEX 255
-#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S 0
-#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
-#define VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset Source: VFR */
-#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
-#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
+#define E800_VFPE_MRTEIDXMASK1(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
+#define E800_VFPE_MRTEIDXMASK1_MAX_INDEX 255
+#define E800_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S 0
+#define E800_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
+#define E800_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset Source: VFR */
+#define E800_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
+#define E800_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
#define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */
#define VFPE_TCPNOWTIMER1_TCP_NOW_S 0
#define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
@@ -9484,5 +9613,1646 @@
#define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)
#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20
#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
+#define E830_GL_QRX_CONTEXT_CTL 0x00296640 /* Reset Source: CORER */
+#define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_S 0
+#define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_M MAKEMASK(0xFFF, 0)
+#define E830_GL_QRX_CONTEXT_CTL_CMD_S 16
+#define E830_GL_QRX_CONTEXT_CTL_CMD_M MAKEMASK(0x7, 16)
+#define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_S 19
+#define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_M BIT(19)
+#define E830_GL_QRX_CONTEXT_DATA(_i) (0x00296620 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_QRX_CONTEXT_DATA_MAX_INDEX 7
+#define E830_GL_QRX_CONTEXT_DATA_DATA_S 0
+#define E830_GL_QRX_CONTEXT_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_QRX_CONTEXT_STAT 0x00296644 /* Reset Source: CORER */
+#define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_S 0
+#define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_M BIT(0)
+#define E830_GL_RCB_INTERNAL(_i) (0x00122600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GL_RCB_INTERNAL_MAX_INDEX 63
+#define E830_GL_RCB_INTERNAL_INTERNAL_S 0
+#define E830_GL_RCB_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_RLAN_INTERNAL(_i) (0x00296700 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GL_RLAN_INTERNAL_MAX_INDEX 63
+#define E830_GL_RLAN_INTERNAL_INTERNAL_S 0
+#define E830_GL_RLAN_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS 0x002D30F0 /* Reset Source: CORER */
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_DBLQ_S 0
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_DBLQ_M MAKEMASK(0xFF, 0)
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_FDBL_S 8
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_FDBL_M MAKEMASK(0xFF, 8)
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_TXT_S 16
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 16)
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS 0x002D30F4 /* Reset Source: CORER */
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_DBLQ_S 0
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_DBLQ_M MAKEMASK(0x3F, 0)
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_FDBL_S 6
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_FDBL_M MAKEMASK(0x3F, 6)
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_TXT_S 12
+#define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 12)
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS 0x002D30F8 /* Reset Source: CORER */
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_S 0
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_M MAKEMASK(0xFF, 0)
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_S 8
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 8)
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS 0x002D30FC /* Reset Source: CORER */
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_S 0
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_M MAKEMASK(0x3F, 0)
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_S 6
+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 6)
+#define E830_GLQTX_TXTIME_DBELL_LSB(_DBQM) (0x002E0000 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_DBELL_LSB_MAX_INDEX 16383
+#define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLQTX_TXTIME_DBELL_MSB(_DBQM) (0x002E0004 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_DBELL_MSB_MAX_INDEX 16383
+#define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTCLAN_CQ_CNTX2_SRC_VSI_S 18
+#define E830_GLTCLAN_CQ_CNTX2_SRC_VSI_M MAKEMASK(0x3FF, 18)
+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS 0x002D320C /* Reset Source: CORER */
+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_S 0
+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_M MAKEMASK(0xFF, 0)
+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_S 8
+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_M MAKEMASK(0xFF, 8)
+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS 0x002D3210 /* Reset Source: CORER */
+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_S 0
+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_M MAKEMASK(0x3F, 0)
+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_S 6
+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_M MAKEMASK(0x3F, 6)
+#define E830_GLTXTIME_FETCH_PROFILE(_i, _j) (0x002D3500 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...15 */ /* Reset Source: CORER */
+#define E830_GLTXTIME_FETCH_PROFILE_MAX_INDEX 15
+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_S 0
+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M MAKEMASK(0x1FF, 0)
+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_S 9
+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_M MAKEMASK(0x7F, 9)
+#define E830_GLTXTIME_OUTST_REQ_CNTL 0x002D3214 /* Reset Source: CORER */
+#define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_S 0
+#define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_M MAKEMASK(0x3FF, 0)
+#define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_S 10
+#define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_M MAKEMASK(0x3FF, 10)
+#define E830_GLTXTIME_QTX_CNTX_CTL 0x002D3204 /* Reset Source: CORER */
+#define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_S 0
+#define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x7FF, 0)
+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_S 16
+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16)
+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_S 19
+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_M BIT(19)
+#define E830_GLTXTIME_QTX_CNTX_DATA(_i) (0x002D3104 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
+#define E830_GLTXTIME_QTX_CNTX_DATA_MAX_INDEX 6
+#define E830_GLTXTIME_QTX_CNTX_DATA_DATA_S 0
+#define E830_GLTXTIME_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTXTIME_QTX_CNTX_STAT 0x002D3208 /* Reset Source: CORER */
+#define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_S 0
+#define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)
+#define E830_GLTXTIME_TS_CFG 0x002D3100 /* Reset Source: CORER */
+#define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_S 0
+#define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_M BIT(0)
+#define E830_GLTXTIME_TS_CFG_STORAGE_MODE_S 2
+#define E830_GLTXTIME_TS_CFG_STORAGE_MODE_M MAKEMASK(0x7, 2)
+#define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_S 5
+#define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_M MAKEMASK(0x1FFF, 5)
+#define E830_MBX_PF_DEC_ERR 0x00234100 /* Reset Source: CORER */
+#define E830_MBX_PF_DEC_ERR_DEC_ERR_S 0
+#define E830_MBX_PF_DEC_ERR_DEC_ERR_M BIT(0)
+#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH 0x00234000 /* Reset Source: CORER */
+#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_S 0
+#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_M MAKEMASK(0x3FF, 0)
+#define E830_MBX_VF_DEC_TRIG(_VF) (0x00233800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_MBX_VF_DEC_TRIG_MAX_INDEX 255
+#define E830_MBX_VF_DEC_TRIG_DEC_S 0
+#define E830_MBX_VF_DEC_TRIG_DEC_M MAKEMASK(0x3FF, 0)
+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(_VF) (0x00233000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MAX_INDEX 255
+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_S 0
+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_M MAKEMASK(0x3FF, 0)
+#define E830_GLRCB_AG_ARBITER_CONFIG 0x00122500 /* Reset Source: CORER */
+#define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_S 0
+#define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0xFFFFF, 0)
+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG 0x00122518 /* Reset Source: CORER */
+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_S 0
+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0x7F, 0)
+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_S 7
+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_M BIT(7)
+#define E830_GLRCB_AG_DCB_NODE_CONFIG(_i) (0x00122510 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GLRCB_AG_DCB_NODE_CONFIG_MAX_INDEX 1
+#define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_S 0
+#define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_M MAKEMASK(0xF, 0)
+#define E830_GLRCB_AG_DCB_NODE_STATE(_i) (0x00122508 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GLRCB_AG_DCB_NODE_STATE_MAX_INDEX 1
+#define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_S 0
+#define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_M MAKEMASK(0xFF, 0)
+#define E830_GLRCB_AG_NODE_CONFIG(_i) (0x001224E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GLRCB_AG_NODE_CONFIG_MAX_INDEX 7
+#define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_S 0
+#define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_M MAKEMASK(0x7F, 0)
+#define E830_GLRCB_AG_NODE_STATE(_i) (0x001224C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GLRCB_AG_NODE_STATE_MAX_INDEX 7
+#define E830_GLRCB_AG_NODE_STATE_CREDITS_S 0
+#define E830_GLRCB_AG_NODE_STATE_CREDITS_M MAKEMASK(0xFFFFF, 0)
+#define E830_PRT_AG_PORT_FC_MAP 0x00122520 /* Reset Source: CORER */
+#define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_S 0
+#define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_M MAKEMASK(0xFF, 0)
+#define E830_GL_FW_LOGS_CTL 0x000827F8 /* Reset Source: POR */
+#define E830_GL_FW_LOGS_CTL_PAGE_SELECT_S 0
+#define E830_GL_FW_LOGS_CTL_PAGE_SELECT_M MAKEMASK(0x3FF, 0)
+#define E830_GL_FW_LOGS_STS 0x000827FC /* Reset Source: POR */
+#define E830_GL_FW_LOGS_STS_MAX_PAGE_S 0
+#define E830_GL_FW_LOGS_STS_MAX_PAGE_M MAKEMASK(0x3FF, 0)
+#define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_S 31
+#define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_M BIT(31)
+#define E830_GL_RTCTL 0x000827F0 /* Reset Source: POR */
+#define E830_GL_RTCTL_RTCTL_S 0
+#define E830_GL_RTCTL_RTCTL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_RTCTM 0x000827F4 /* Reset Source: POR */
+#define E830_GL_RTCTM_RTCTM_S 0
+#define E830_GL_RTCTM_RTCTM_M MAKEMASK(0xFFFF, 0)
+#define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_S 3
+#define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_M BIT(3)
+#define E830_GLPE_TSCD_NUM_PQS 0x0051E2FC /* Reset Source: CORER */
+#define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_S 0
+#define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTPB_100G_RPB_FC_THRESH2 0x0009972C /* Reset Source: CORER */
+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_S 0
+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_S 16
+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_GLTPB_100G_RPB_FC_THRESH3 0x00099730 /* Reset Source: CORER */
+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_S 0
+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_S 16
+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PORT_TIMER_SEL(_i) (0x00088BE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_PORT_TIMER_SEL_MAX_INDEX 7
+#define E830_PORT_TIMER_SEL_TIMER_SEL_S 0
+#define E830_PORT_TIMER_SEL_TIMER_SEL_M BIT(0)
+#define E830_GL_RDPU_CNTRL_CHECKSUM_COMPLETE_INV_S 22
+#define E830_GL_RDPU_CNTRL_CHECKSUM_COMPLETE_INV_M BIT(22)
+#define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT 0x001E2280 /* Reset Source: GLOBR */
+#define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_S 0
+#define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTTSYN_TXTIME_H(_i) (0x001E5800 + ((_i) * 32)) /* _i=0...63 */ /* Reset Source: GLOBR */
+#define E830_PRTTSYN_TXTIME_H_MAX_INDEX 63
+#define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_S 0
+#define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_M MAKEMASK(0xFF, 0)
+#define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 32)) /* _i=0...63 */ /* Reset Source: GLOBR */
+#define E830_PRTTSYN_TXTIME_L_MAX_INDEX 63
+#define E830_PRTTSYN_TXTIME_L_TX_VALID_S 0
+#define E830_PRTTSYN_TXTIME_L_TX_VALID_M BIT(0)
+#define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_S 1
+#define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_M MAKEMASK(0x7FFFFFFF, 1)
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN 0x000FD200 /* Reset Source: CORER */
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_FROM_Q_NOT_ALLOWED_S 0
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_FROM_Q_NOT_ALLOWED_M BIT(0)
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_RANGE_VIOLATION_S 1
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_RANGE_VIOLATION_M BIT(1)
+#define E830_GL_MDET_RX_FIFO 0x00296840 /* Reset Source: CORER */
+#define E830_GL_MDET_RX_FIFO_FUNC_NUM_S 0
+#define E830_GL_MDET_RX_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
+#define E830_GL_MDET_RX_FIFO_PF_NUM_S 10
+#define E830_GL_MDET_RX_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
+#define E830_GL_MDET_RX_FIFO_FUNC_TYPE_S 13
+#define E830_GL_MDET_RX_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
+#define E830_GL_MDET_RX_FIFO_MAL_TYPE_S 15
+#define E830_GL_MDET_RX_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
+#define E830_GL_MDET_RX_FIFO_FIFO_FULL_S 20
+#define E830_GL_MDET_RX_FIFO_FIFO_FULL_M BIT(20)
+#define E830_GL_MDET_RX_FIFO_VALID_S 21
+#define E830_GL_MDET_RX_FIFO_VALID_M BIT(21)
+#define E830_GL_MDET_RX_FIFO_EVENT_CNT_S 24
+#define E830_GL_MDET_RX_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
+#define E830_GL_MDET_RX_PF_CNT(_i) (0x00296800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_RX_PF_CNT_MAX_INDEX 7
+#define E830_GL_MDET_RX_PF_CNT_CNT_S 0
+#define E830_GL_MDET_RX_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_RX_VF(_i) (0x00296820 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_RX_VF_MAX_INDEX 7
+#define E830_GL_MDET_RX_VF_VF_MAL_EVENT_S 0
+#define E830_GL_MDET_RX_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_TX_PQM_FIFO 0x002D4B00 /* Reset Source: CORER */
+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_S 0
+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
+#define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_S 10
+#define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_S 13
+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
+#define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_S 15
+#define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
+#define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_S 20
+#define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_M BIT(20)
+#define E830_GL_MDET_TX_PQM_FIFO_VALID_S 21
+#define E830_GL_MDET_TX_PQM_FIFO_VALID_M BIT(21)
+#define E830_GL_MDET_TX_PQM_FIFO_EVENT_CNT_S 24
+#define E830_GL_MDET_TX_PQM_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
+#define E830_GL_MDET_TX_PQM_PF_CNT(_i) (0x002D4AC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_TX_PQM_PF_CNT_MAX_INDEX 7
+#define E830_GL_MDET_TX_PQM_PF_CNT_CNT_S 0
+#define E830_GL_MDET_TX_PQM_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_TX_PQM_VF(_i) (0x002D4AE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_TX_PQM_VF_MAX_INDEX 7
+#define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_S 0
+#define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_TX_TCLAN_FIFO 0x000FCFD0 /* Reset Source: CORER */
+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_S 0
+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
+#define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_S 10
+#define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_S 13
+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
+#define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_S 15
+#define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
+#define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_S 20
+#define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_M BIT(20)
+#define E830_GL_MDET_TX_TCLAN_FIFO_VALID_S 21
+#define E830_GL_MDET_TX_TCLAN_FIFO_VALID_M BIT(21)
+#define E830_GL_MDET_TX_TCLAN_FIFO_EVENT_CNT_S 24
+#define E830_GL_MDET_TX_TCLAN_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
+#define E830_GL_MDET_TX_TCLAN_PF_CNT(_i) (0x000FCF90 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_TX_TCLAN_PF_CNT_MAX_INDEX 7
+#define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_S 0
+#define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_TX_TCLAN_VF(_i) (0x000FCFB0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_TX_TCLAN_VF_MAX_INDEX 7
+#define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_S 0
+#define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_TX_TDPU_FIFO 0x00049D80 /* Reset Source: CORER */
+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_S 0
+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
+#define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_S 10
+#define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_S 13
+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
+#define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_S 15
+#define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
+#define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_S 20
+#define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_M BIT(20)
+#define E830_GL_MDET_TX_TDPU_FIFO_VALID_S 21
+#define E830_GL_MDET_TX_TDPU_FIFO_VALID_M BIT(21)
+#define E830_GL_MDET_TX_TDPU_FIFO_EVENT_CNT_S 24
+#define E830_GL_MDET_TX_TDPU_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
+#define E830_GL_MDET_TX_TDPU_PF_CNT(_i) (0x00049D40 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_TX_TDPU_PF_CNT_MAX_INDEX 7
+#define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_S 0
+#define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_TX_TDPU_VF(_i) (0x00049D60 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_TX_TDPU_VF_MAX_INDEX 7
+#define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_S 0
+#define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MNG_ECDSA_PUBKEY_HIGH(_i) (0x00083400 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
+#define E830_GL_MNG_ECDSA_PUBKEY_HIGH_MAX_INDEX 11
+#define E830_GL_MNG_ECDSA_PUBKEY_HIGH_GL_MNG_ECDSA_PUBKEY_S 0
+#define E830_GL_MNG_ECDSA_PUBKEY_HIGH_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MNG_ECDSA_PUBKEY_LOW(_i) (0x00083300 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
+#define E830_GL_MNG_ECDSA_PUBKEY_LOW_MAX_INDEX 11
+#define E830_GL_MNG_ECDSA_PUBKEY_LOW_GL_MNG_ECDSA_PUBKEY_S 0
+#define E830_GL_MNG_ECDSA_PUBKEY_LOW_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_PPRS_RX_SIZE_CTRL_0(_i) (0x00084900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_INDEX 1
+#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_S 16
+#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
+#define E830_GL_PPRS_RX_SIZE_CTRL_1(_i) (0x00085900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_INDEX 1
+#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_S 16
+#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
+#define E830_GL_PPRS_RX_SIZE_CTRL_2(_i) (0x00086900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_INDEX 1
+#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_S 16
+#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
+#define E830_GL_PPRS_RX_SIZE_CTRL_3(_i) (0x00087900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_INDEX 1
+#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_S 16
+#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP 0x00200740 /* Reset Source: CORER */
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00200744 /* Reset Source: CORER */
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16)
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24
+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24)
+#define E830_GL_RPRS_PROT_ID_MAP(_i) (0x00200800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_GL_RPRS_PROT_ID_MAP_MAX_INDEX 255
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_S 0
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0)
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_S 8
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8)
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_S 16
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16)
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_S 24
+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL(_i) (0x00201000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_MAX_INDEX 63
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28)
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30
+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30)
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL 0x00200748 /* Reset Source: CORER */
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0)
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1)
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2)
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3)
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4)
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5
+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP 0x00203A04 /* Reset Source: CORER */
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00203A08 /* Reset Source: CORER */
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16)
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24
+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24)
+#define E830_GL_TPRS_PROT_ID_MAP(_i) (0x00202200 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_GL_TPRS_PROT_ID_MAP_MAX_INDEX 255
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_S 0
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0)
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_S 8
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8)
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_S 16
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16)
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_S 24
+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL(_i) (0x00202A00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_MAX_INDEX 63
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28)
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30
+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30)
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL 0x00203A00 /* Reset Source: CORER */
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0)
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1)
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2)
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3)
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4)
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5
+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5)
+#define E830_PRT_TDPU_TX_SIZE_CTRL 0x00049D20 /* Reset Source: CORER */
+#define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_S 16
+#define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
+#define E830_PRT_TPB_RX_LB_SIZE_CTRL 0x00099740 /* Reset Source: CORER */
+#define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_S 16
+#define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE(_DBQM) (0x04000008 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_MAX_INDEX 16383
+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE(_DBQM) (0x0400000C + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_MAX_INDEX 16383
+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_S 8
+#define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_M BIT(8)
+#define E830_PF0INT_OICR_PSM_PAGE_PQM_DBL_TO_S 9
+#define E830_PF0INT_OICR_PSM_PAGE_PQM_DBL_TO_M BIT(9)
+#define E830_PF0INT_OICR_PSM_PAGE_RSV5_S 10
+#define E830_PF0INT_OICR_PSM_PAGE_RSV5_M BIT(10)
+#define E830_GL_HIBA(_i) (0x00081000 + ((_i) * 4)) /* _i=0...1023 */ /* Reset Source: EMPR */
+#define E830_GL_HIBA_MAX_INDEX 1023
+#define E830_GL_HIBA_GL_HIBA_S 0
+#define E830_GL_HIBA_GL_HIBA_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_HICR 0x00082040 /* Reset Source: EMPR */
+#define E830_GL_HICR_C_S 1
+#define E830_GL_HICR_C_M BIT(1)
+#define E830_GL_HICR_SV_S 2
+#define E830_GL_HICR_SV_M BIT(2)
+#define E830_GL_HICR_EV_S 3
+#define E830_GL_HICR_EV_M BIT(3)
+#define E830_GL_HICR_EN 0x00082044 /* Reset Source: EMPR */
+#define E830_GL_HICR_EN_EN_S 0
+#define E830_GL_HICR_EN_EN_M BIT(0)
+#define E830_GL_HIDA(_i) (0x00082000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: EMPR */
+#define E830_GL_HIDA_MAX_INDEX 15
+#define E830_GL_HIDA_GL_HIDB_S 0
+#define E830_GL_HIDA_GL_HIDB_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_M MAKEMASK(0xF, 18)
+#define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_M MAKEMASK(0xF, 18)
+#define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_M MAKEMASK(0xF, 18)
+#define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_M MAKEMASK(0xF, 18)
+#define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_M MAKEMASK(0xF, 18)
+#define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_M MAKEMASK(0xF, 18)
+#define E830_GLFLXP_RXDID_FLX_WRD_6(_i) (0x0045CE00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GLFLXP_RXDID_FLX_WRD_6_MAX_INDEX 63
+#define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_S 0
+#define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_M MAKEMASK(0xFF, 0)
+#define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_S 8
+#define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
+#define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_M BIT(18)
+#define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_S 19
+#define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_M MAKEMASK(0x7, 19)
+#define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_S 30
+#define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_M MAKEMASK(0x3, 30)
+#define E830_GLFLXP_RXDID_FLX_WRD_7(_i) (0x0045CF00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GLFLXP_RXDID_FLX_WRD_7_MAX_INDEX 63
+#define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_S 0
+#define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_M MAKEMASK(0xFF, 0)
+#define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_S 8
+#define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
+#define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_M BIT(18)
+#define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_S 19
+#define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_M MAKEMASK(0x7, 19)
+#define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_S 30
+#define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_M MAKEMASK(0x3, 30)
+#define E830_GLFLXP_RXDID_FLX_WRD_8(_i) (0x0045D500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
+#define E830_GLFLXP_RXDID_FLX_WRD_8_MAX_INDEX 63
+#define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_S 0
+#define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_M MAKEMASK(0xFF, 0)
+#define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_S 8
+#define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
+#define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_S 18
+#define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_M BIT(18)
+#define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_S 19
+#define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_M MAKEMASK(0x7, 19)
+#define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_S 30
+#define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_M MAKEMASK(0x3, 30)
+#define E830_GL_FW_LOGS(_i) (0x00082800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: POR */
+#define E830_GL_FW_LOGS_MAX_INDEX 255
+#define E830_GL_FW_LOGS_GL_FW_LOGS_S 0
+#define E830_GL_FW_LOGS_GL_FW_LOGS_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_FWSTS_FWABS_S 10
+#define E830_GL_FWSTS_FWABS_M MAKEMASK(0x3, 10)
+#define E830_GL_FWSTS_FW_FAILOVER_TRIG_S 12
+#define E830_GL_FWSTS_FW_FAILOVER_TRIG_M BIT(12)
+#define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_S 19
+#define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_M MAKEMASK(0x3, 19)
+#define E830_GLGEN_RSTAT_EMPR_TYPE_S 21
+#define E830_GLGEN_RSTAT_EMPR_TYPE_M BIT(21)
+#define E830_GLPCI_PLATFORM_INFO 0x0009DDC4 /* Reset Source: POR */
+#define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_S 0
+#define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_M MAKEMASK(0xFF, 0)
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_FROM_Q_NOT_ALLOWED_S 21
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_FROM_Q_NOT_ALLOWED_M BIT(21)
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_RANGE_VIOLATION_S 22
+#define E830_GL_MDCK_TDAT_TCLAN_TSYN_PKT_RANGE_VIOLATION_M BIT(22)
+#define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_S 23
+#define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_M BIT(23)
+#define E830_GL_TPB_LOCAL_TOPO 0x000996F4 /* Reset Source: CORER */
+#define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_S 0
+#define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_M BIT(0)
+#define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_S 1
+#define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_M MAKEMASK(0x3, 1)
+#define E830_GL_TPB_PM_RESET 0x000996F0 /* Reset Source: CORER */
+#define E830_GL_TPB_PM_RESET_MAC_PM_RESET_S 0
+#define E830_GL_TPB_PM_RESET_MAC_PM_RESET_M BIT(0)
+#define E830_GL_TPB_PM_RESET_RPB_PM_RESET_S 1
+#define E830_GL_TPB_PM_RESET_RPB_PM_RESET_M BIT(1)
+#define E830_GLTPB_100G_MAC_FC_THRESH1 0x00099724 /* Reset Source: CORER */
+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_S 0
+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_S 16
+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_GLTPB_100G_RPB_FC_THRESH0 0x0009963C /* Reset Source: CORER */
+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_S 0
+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_S 16
+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_GLTPB_100G_RPB_FC_THRESH1 0x00099728 /* Reset Source: CORER */
+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_S 0
+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_S 16
+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_S 12
+#define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_M MAKEMASK(0xFFFF, 12)
+#define E830_PF0INT_OICR_PSM_PTM_COMP_S 8
+#define E830_PF0INT_OICR_PSM_PTM_COMP_M BIT(8)
+#define E830_PF0INT_OICR_PSM_PQM_DBL_TO_S 9
+#define E830_PF0INT_OICR_PSM_PQM_DBL_TO_M BIT(9)
+#define E830_PF0INT_OICR_PSM_RSV5_S 10
+#define E830_PF0INT_OICR_PSM_RSV5_M BIT(10)
+#define E830_PFINT_OICR_PTM_COMP_S 8
+#define E830_PFINT_OICR_PTM_COMP_M BIT(8)
+#define E830_PFINT_OICR_PQM_DBL_TO_S 9
+#define E830_PFINT_OICR_PQM_DBL_TO_M BIT(9)
+#define E830_PFINT_OICR_RSV5_S 10
+#define E830_PFINT_OICR_RSV5_M BIT(10)
+#define E830_QRX_CTRL_IDE_S 27
+#define E830_QRX_CTRL_IDE_M BIT(27)
+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA 0x001E3854 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH 0x001E3864 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0
+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16
+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA 0x001E3858 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH 0x001E3868 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0
+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16
+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA 0x001E385C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH 0x001E386C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0
+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16
+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA 0x001E3860 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH 0x001E3870 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0
+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16
+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_COMMAND_CONFIG 0x001E3808 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_S 0
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_M BIT(0)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_S 1
+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_M BIT(1)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_S 4
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_M BIT(4)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAD_EN_S 5
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAD_EN_M BIT(5)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_S 6
+#define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_M BIT(6)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_S 7
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_M BIT(7)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_S 8
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_S 9
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_LOOPBACK_EN_S 10
+#define E830_PRTMAC_200G_COMMAND_CONFIG_LOOPBACK_EN_M BIT(10)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_S 11
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_M BIT(11)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_S 12
+#define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_M BIT(12)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_S 13
+#define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ERR_DISC_S 14
+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ERR_DISC_M BIT(14)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_S 15
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_M BIT(15)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_SEND_IDLE_S 16
+#define E830_PRTMAC_200G_COMMAND_CONFIG_SEND_IDLE_M BIT(16)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_S 17
+#define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_M BIT(17)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_S 19
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_M BIT(19)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20
+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_S 21
+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_S 22
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_M BIT(22)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_S 25
+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_S 26
+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_S 27
+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27)
+#define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_S 31
+#define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_M BIT(31)
+#define E830_PRTMAC_200G_CRC_INV_M 0x001E384C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_S 0
+#define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_200G_FRM_LENGTH 0x001E3814 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_S 0
+#define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_S 16
+#define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_HASHTABLE_LOAD 0x001E382C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_S 0
+#define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_M MAKEMASK(0x3F, 0)
+#define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_S 8
+#define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_M BIT(8)
+#define E830_PRTMAC_200G_MAC_ADDR_0 0x001E380C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_S 0
+#define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_200G_MAC_ADDR_1 0x001E3810 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_S 0
+#define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS 0x001E3830 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_S 0
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0)
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1)
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2)
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5)
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6)
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7
+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7)
+#define E830_PRTMAC_200G_MDIO_COMMAND 0x001E3834 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_S 0
+#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_MDIO_COMMAND_RESERVED_2_S 16
+#define E830_PRTMAC_200G_MDIO_COMMAND_RESERVED_2_M MAKEMASK(0x7FFF, 16)
+#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_BUSY_S 31
+#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_BUSY_M BIT(31)
+#define E830_PRTMAC_200G_MDIO_DATA 0x001E3838 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_S 0
+#define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_MDIO_DATA_RESERVED_2_S 16
+#define E830_PRTMAC_200G_MDIO_DATA_RESERVED_2_M MAKEMASK(0x7FFF, 16)
+#define E830_PRTMAC_200G_MDIO_DATA_MDIO_BUSY_S 31
+#define E830_PRTMAC_200G_MDIO_DATA_MDIO_BUSY_M BIT(31)
+#define E830_PRTMAC_200G_MDIO_REGADDR 0x001E383C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_S 0
+#define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_200G_REVISION 0x001E3800 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_REVISION_CORE_REVISION_S 0
+#define E830_PRTMAC_200G_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_200G_REVISION_CORE_VERSION_S 8
+#define E830_PRTMAC_200G_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8)
+#define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_S 16
+#define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_RX_PAUSE_STATUS 0x001E3874 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0
+#define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_200G_SCRATCH 0x001E3804 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_SCRATCH_SCRATCH_S 0
+#define E830_PRTMAC_200G_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_200G_STATUS 0x001E3840 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_S 0
+#define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_M BIT(0)
+#define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_S 1
+#define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_M BIT(1)
+#define E830_PRTMAC_200G_STATUS_PHY_LOS_S 2
+#define E830_PRTMAC_200G_STATUS_PHY_LOS_M BIT(2)
+#define E830_PRTMAC_200G_STATUS_TS_AVAIL_S 3
+#define E830_PRTMAC_200G_STATUS_TS_AVAIL_M BIT(3)
+#define E830_PRTMAC_200G_STATUS_RESERVED_5_S 4
+#define E830_PRTMAC_200G_STATUS_RESERVED_5_M BIT(4)
+#define E830_PRTMAC_200G_STATUS_TX_EMPTY_S 5
+#define E830_PRTMAC_200G_STATUS_TX_EMPTY_M BIT(5)
+#define E830_PRTMAC_200G_STATUS_RX_EMPTY_S 6
+#define E830_PRTMAC_200G_STATUS_RX_EMPTY_M BIT(6)
+#define E830_PRTMAC_200G_STATUS_RESERVED1_S 7
+#define E830_PRTMAC_200G_STATUS_RESERVED1_M BIT(7)
+#define E830_PRTMAC_200G_STATUS_TX_ISIDLE_S 8
+#define E830_PRTMAC_200G_STATUS_TX_ISIDLE_M BIT(8)
+#define E830_PRTMAC_200G_STATUS_RESERVED2_S 9
+#define E830_PRTMAC_200G_STATUS_RESERVED2_M MAKEMASK(0x7FFFFF, 9)
+#define E830_PRTMAC_200G_TS_TIMESTAMP 0x001E387C /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_S 0
+#define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS 0x001E3820 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0
+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16
+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_200G_TX_IPG_LENGTH 0x001E3844 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_S 0
+#define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x7F, 0)
+#define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_S 19
+#define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_M MAKEMASK(0x1FFF, 19)
+#define E830_PRTMAC_200G_XIF_MODE 0x001E3880 /* Reset Source: GLOBR */
+#define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_S 0
+#define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_M MAKEMASK(0x1F, 0)
+#define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_S 5
+#define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_M BIT(5)
+#define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_S 17
+#define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_M BIT(17)
+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_S 18
+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_M BIT(18)
+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_S 19
+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_M BIT(19)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0 0x001E3C00 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0_APPROVED_SW_ADDR_MAC_100G_0_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0_APPROVED_SW_ADDR_MAC_100G_0_M MAKEMASK(0x3F, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1 0x001E3C20 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1_APPROVED_SW_ADDR_MAC_100G_1_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1_APPROVED_SW_ADDR_MAC_100G_1_M MAKEMASK(0x3F, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2 0x001E3C40 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2_APPROVED_SW_ADDR_MAC_100G_2_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2_APPROVED_SW_ADDR_MAC_100G_2_M MAKEMASK(0x3F, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3 0x001E3C60 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3_APPROVED_SW_ADDR_MAC_100G_3_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3_APPROVED_SW_ADDR_MAC_100G_3_M MAKEMASK(0x3F, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0 0x001E3C80 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0_APPROVED_SW_ADDR_MAC_200G_0_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0_APPROVED_SW_ADDR_MAC_200G_0_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1 0x001E3CA0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1_APPROVED_SW_ADDR_MAC_200G_1_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1_APPROVED_SW_ADDR_MAC_200G_1_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2 0x001E3CC0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2_APPROVED_SW_ADDR_MAC_200G_2_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2_APPROVED_SW_ADDR_MAC_200G_2_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3 0x001E3CE0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3_APPROVED_SW_ADDR_MAC_200G_3_S 0
+#define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3_APPROVED_SW_ADDR_MAC_200G_3_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_CF_GEN_STATUS 0x001E33C0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_S 0
+#define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_M BIT(0)
+#define E830_PRTMAC_CL01_PAUSE_QUANTA 0x001E32A0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL01_QUANTA_THRESH 0x001E3320 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0
+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16
+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL23_PAUSE_QUANTA 0x001E32C0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL23_QUANTA_THRESH 0x001E3340 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0
+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16
+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL45_PAUSE_QUANTA 0x001E32E0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL45_QUANTA_THRESH 0x001E3360 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0
+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16
+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL67_PAUSE_QUANTA 0x001E3300 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0
+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16
+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_CL67_QUANTA_THRESH 0x001E3380 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0
+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16
+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_COMMAND_CONFIG 0x001E3040 /* Reset Source: GLOBR */
+#define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_S 0
+#define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_M BIT(0)
+#define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_S 1
+#define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_M BIT(1)
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_S 3
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_M BIT(3)
+#define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_S 4
+#define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_M BIT(4)
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_S 5
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_M BIT(5)
+#define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_S 6
+#define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_M BIT(6)
+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_S 7
+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_M BIT(7)
+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_S 8
+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8)
+#define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_S 9
+#define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9)
+#define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_S 10
+#define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_M BIT(10)
+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_S 11
+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_M BIT(11)
+#define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_S 12
+#define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_M BIT(12)
+#define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_S 13
+#define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13)
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_S 14
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_M BIT(14)
+#define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_S 15
+#define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_M BIT(15)
+#define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__S 16
+#define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__M BIT(16)
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_S 17
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_M BIT(17)
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_S 18
+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_M BIT(18)
+#define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_S 19
+#define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_M BIT(19)
+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20
+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20)
+#define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_S 21
+#define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21)
+#define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_S 22
+#define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_M BIT(22)
+#define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_S 23
+#define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_M BIT(23)
+#define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_S 24
+#define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_M BIT(24)
+#define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_S 25
+#define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25)
+#define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_S 26
+#define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26)
+#define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_S 27
+#define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27)
+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_S 28
+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_M BIT(28)
+#define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_S 29
+#define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_M BIT(29)
+#define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_S 30
+#define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_M BIT(30)
+#define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_S 31
+#define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_M BIT(31)
+#define E830_PRTMAC_CRC_INV_M 0x001E3260 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_S 0
+#define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_CRC_MODE 0x001E3240 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_S 16
+#define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_M BIT(16)
+#define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_S 18
+#define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_M BIT(18)
+#define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_S 19
+#define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_M BIT(19)
+#define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_S 20
+#define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_M BIT(20)
+#define E830_PRTMAC_CSR_TIMEOUT_CFG 0x001E3D00 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CSR_TIMEOUT_CFG_CSR_TIMEOUT_EN_S 0
+#define E830_PRTMAC_CSR_TIMEOUT_CFG_CSR_TIMEOUT_EN_M BIT(0)
+#define E830_PRTMAC_CTL_RX_CFG 0x001E2160 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CTL_RX_CFG_SUB_CRC_STAT_S 0
+#define E830_PRTMAC_CTL_RX_CFG_SUB_CRC_STAT_M BIT(0)
+#define E830_PRTMAC_CTL_RX_CFG_FRM_DROP_FOR_STAT_MODE_S 1
+#define E830_PRTMAC_CTL_RX_CFG_FRM_DROP_FOR_STAT_MODE_M MAKEMASK(0x3, 1)
+#define E830_PRTMAC_CTL_RX_CFG_MAC_PAC_AFULL_TRSH_S 3
+#define E830_PRTMAC_CTL_RX_CFG_MAC_PAC_AFULL_TRSH_M MAKEMASK(0x7, 3)
+#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE 0x001E2180 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S 0
+#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
+#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE 0x001E21A0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S 0
+#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
+#define E830_PRTMAC_FRM_LENGTH 0x001E30A0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_S 0
+#define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_FRM_LENGTH_TX_MTU_S 16
+#define E830_PRTMAC_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_MAC_ADDR_0 0x001E3060 /* Reset Source: GLOBR */
+#define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_S 0
+#define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_MAC_ADDR_1 0x001E3080 /* Reset Source: GLOBR */
+#define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_S 0
+#define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_MDIO_CFG_STATUS 0x001E3180 /* Reset Source: GLOBR */
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_S 0
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0)
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1)
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2)
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5)
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6)
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7
+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7)
+#define E830_PRTMAC_MDIO_COMMAND 0x001E31A0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_S 0
+#define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_MDIO_COMMAND_RESERVED_2_S 16
+#define E830_PRTMAC_MDIO_COMMAND_RESERVED_2_M MAKEMASK(0x7FFF, 16)
+#define E830_PRTMAC_MDIO_COMMAND_MDIO_BUSY_S 31
+#define E830_PRTMAC_MDIO_COMMAND_MDIO_BUSY_M BIT(31)
+#define E830_PRTMAC_MDIO_DATA 0x001E31C0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_MDIO_DATA_MDIO_DATA_S 0
+#define E830_PRTMAC_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_MDIO_DATA_RESERVED_2_S 16
+#define E830_PRTMAC_MDIO_DATA_RESERVED_2_M MAKEMASK(0x7FFF, 16)
+#define E830_PRTMAC_MDIO_DATA_MDIO_BUSY_S 31
+#define E830_PRTMAC_MDIO_DATA_MDIO_BUSY_M BIT(31)
+#define E830_PRTMAC_MDIO_REGADDR 0x001E31E0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_S 0
+#define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_REVISION 0x001E3000 /* Reset Source: GLOBR */
+#define E830_PRTMAC_REVISION_CORE_REVISION_S 0
+#define E830_PRTMAC_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_REVISION_CORE_VERSION_S 8
+#define E830_PRTMAC_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8)
+#define E830_PRTMAC_REVISION_CUSTOMER_VERSION_S 16
+#define E830_PRTMAC_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT 0x001E24C0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT_RX_OFLOW_PKT_DRP_BSOP_CNT_S 0
+#define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT_RX_OFLOW_PKT_DRP_BSOP_CNT_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_RX_PAUSE_STATUS 0x001E33A0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0
+#define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0)
+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_S 12
+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 12)
+#define E830_PRTMAC_SCRATCH 0x001E3020 /* Reset Source: GLOBR */
+#define E830_PRTMAC_SCRATCH_SCRATCH_S 0
+#define E830_PRTMAC_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_STATUS 0x001E3200 /* Reset Source: GLOBR */
+#define E830_PRTMAC_STATUS_RX_LOC_FAULT_S 0
+#define E830_PRTMAC_STATUS_RX_LOC_FAULT_M BIT(0)
+#define E830_PRTMAC_STATUS_RX_REM_FAULT_S 1
+#define E830_PRTMAC_STATUS_RX_REM_FAULT_M BIT(1)
+#define E830_PRTMAC_STATUS_PHY_LOS_S 2
+#define E830_PRTMAC_STATUS_PHY_LOS_M BIT(2)
+#define E830_PRTMAC_STATUS_TS_AVAIL_S 3
+#define E830_PRTMAC_STATUS_TS_AVAIL_M BIT(3)
+#define E830_PRTMAC_STATUS_RX_LOWP_S 4
+#define E830_PRTMAC_STATUS_RX_LOWP_M BIT(4)
+#define E830_PRTMAC_STATUS_TX_EMPTY_S 5
+#define E830_PRTMAC_STATUS_TX_EMPTY_M BIT(5)
+#define E830_PRTMAC_STATUS_RX_EMPTY_S 6
+#define E830_PRTMAC_STATUS_RX_EMPTY_M BIT(6)
+#define E830_PRTMAC_STATUS_RX_LINT_FAULT_S 7
+#define E830_PRTMAC_STATUS_RX_LINT_FAULT_M BIT(7)
+#define E830_PRTMAC_STATUS_TX_ISIDLE_S 8
+#define E830_PRTMAC_STATUS_TX_ISIDLE_M BIT(8)
+#define E830_PRTMAC_STATUS_RESERVED_10_S 9
+#define E830_PRTMAC_STATUS_RESERVED_10_M MAKEMASK(0x7FFFFF, 9)
+#define E830_PRTMAC_STATUS_SPARE 0x001E2740 /* Reset Source: GLOBR */
+#define E830_PRTMAC_STATUS_SPARE_DFD_STATUS_SPARE_S 0
+#define E830_PRTMAC_STATUS_SPARE_DFD_STATUS_SPARE_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_TS_RX_PCS_LATENCY 0x001E2220 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_S 0
+#define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_TS_TIMESTAMP 0x001E33E0 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_S 0
+#define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_S 0
+#define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_S 0
+#define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PRTMAC_TS_TX_PCS_LATENCY 0x001E2200 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_S 0
+#define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_TX_FIFO_SECTIONS 0x001E3100 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0
+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16
+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_TX_IPG_LENGTH 0x001E3220 /* Reset Source: GLOBR */
+#define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_S 0
+#define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x3F, 0)
+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_S 8
+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_M MAKEMASK(0xFF, 8)
+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_S 16
+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_M MAKEMASK(0xFFFF, 16)
+#define E830_PRTMAC_USER_TX_PAUSE_CNT 0x001E2760 /* Reset Source: GLOBR */
+#define E830_PRTMAC_USER_TX_PAUSE_CNT_USER_TX_PAUSE_CNT_S 0
+#define E830_PRTMAC_USER_TX_PAUSE_CNT_USER_TX_PAUSE_CNT_M MAKEMASK(0xFFFF, 0)
+#define E830_PRTMAC_XIF_MODE 0x001E3400 /* Reset Source: GLOBR */
+#define E830_PRTMAC_XIF_MODE_XGMII_ENA_S 0
+#define E830_PRTMAC_XIF_MODE_XGMII_ENA_M BIT(0)
+#define E830_PRTMAC_XIF_MODE_RESERVED_2_S 1
+#define E830_PRTMAC_XIF_MODE_RESERVED_2_M MAKEMASK(0x7, 1)
+#define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_S 4
+#define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_M BIT(4)
+#define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_S 5
+#define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_M BIT(5)
+#define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_S 6
+#define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_M BIT(6)
+#define E830_PRTMAC_XIF_MODE_RESERVED1_S 7
+#define E830_PRTMAC_XIF_MODE_RESERVED1_M BIT(7)
+#define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_S 8
+#define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_M BIT(8)
+#define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_S 9
+#define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_M BIT(9)
+#define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_S 10
+#define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_M BIT(10)
+#define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_S 11
+#define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_M BIT(11)
+#define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_S 12
+#define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_M BIT(12)
+#define E830_PRTMAC_XIF_MODE_RESERVED2_S 13
+#define E830_PRTMAC_XIF_MODE_RESERVED2_M MAKEMASK(0x7, 13)
+#define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_S 16
+#define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_M BIT(16)
+#define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_S 17
+#define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_M BIT(17)
+#define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_S 18
+#define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_M BIT(18)
+#define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_S 19
+#define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_M BIT(19)
+#define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_S 20
+#define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_M BIT(20)
+#define E830_PRTMAC_XIF_MODE_RESERVED3_S 21
+#define E830_PRTMAC_XIF_MODE_RESERVED3_M MAKEMASK(0x7FF, 21)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF 0x001E2700 /* Reset Source: GLOBR */
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF0_S 0
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF0_M MAKEMASK(0xF, 0)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF1_S 4
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF1_M MAKEMASK(0xF, 4)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF2_S 8
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF2_M MAKEMASK(0xF, 8)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF3_S 12
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF3_M MAKEMASK(0xF, 12)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF4_S 16
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF4_M MAKEMASK(0xF, 16)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF5_S 20
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF5_M MAKEMASK(0xF, 20)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF6_S 24
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF6_M MAKEMASK(0xF, 24)
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF7_S 28
+#define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF7_M MAKEMASK(0xF, 28)
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_S 28
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_M BIT(28)
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_S 29
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_M BIT(29)
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_S 30
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_M BIT(30)
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_S 31
+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_M BIT(31)
+#define E830_GL_MDET_HIF_UR_FIFO 0x00096844 /* Reset Source: CORER */
+#define E830_GL_MDET_HIF_UR_FIFO_FUNC_NUM_S 0
+#define E830_GL_MDET_HIF_UR_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
+#define E830_GL_MDET_HIF_UR_FIFO_PF_NUM_S 10
+#define E830_GL_MDET_HIF_UR_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
+#define E830_GL_MDET_HIF_UR_FIFO_FUNC_TYPE_S 13
+#define E830_GL_MDET_HIF_UR_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
+#define E830_GL_MDET_HIF_UR_FIFO_MAL_TYPE_S 15
+#define E830_GL_MDET_HIF_UR_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
+#define E830_GL_MDET_HIF_UR_FIFO_FIFO_FULL_S 20
+#define E830_GL_MDET_HIF_UR_FIFO_FIFO_FULL_M BIT(20)
+#define E830_GL_MDET_HIF_UR_FIFO_VALID_S 21
+#define E830_GL_MDET_HIF_UR_FIFO_VALID_M BIT(21)
+#define E830_GL_MDET_HIF_UR_FIFO_EVENT_CNT_S 24
+#define E830_GL_MDET_HIF_UR_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
+#define E830_GL_MDET_HIF_UR_PF_CNT(_i) (0x00096804 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_HIF_UR_PF_CNT_MAX_INDEX 7
+#define E830_GL_MDET_HIF_UR_PF_CNT_CNT_S 0
+#define E830_GL_MDET_HIF_UR_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GL_MDET_HIF_UR_VF(_i) (0x00096824 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GL_MDET_HIF_UR_VF_MAX_INDEX 7
+#define E830_GL_MDET_HIF_UR_VF_VF_MAL_EVENT_S 0
+#define E830_GL_MDET_HIF_UR_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PF_MDET_HIF_UR 0x00096880 /* Reset Source: CORER */
+#define E830_PF_MDET_HIF_UR_VALID_S 0
+#define E830_PF_MDET_HIF_UR_VALID_M BIT(0)
+#define E830_VM_MDET_TX_TCLAN(_i) (0x000FC348 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
+#define E830_VM_MDET_TX_TCLAN_MAX_INDEX 767
+#define E830_VM_MDET_TX_TCLAN_VALID_S 0
+#define E830_VM_MDET_TX_TCLAN_VALID_M BIT(0)
+#define E830_VP_MDET_HIF_UR(_VF) (0x00096C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_VP_MDET_HIF_UR_MAX_INDEX 255
+#define E830_VP_MDET_HIF_UR_VALID_S 0
+#define E830_VP_MDET_HIF_UR_VALID_M BIT(0)
+#define E830_GLNVM_FLA_GLOBAL_LOCKED_S 7
+#define E830_GLNVM_FLA_GLOBAL_LOCKED_M BIT(7)
+#define E830_DMA_AGENT_AT0 0x000BE268 /* Reset Source: PCIR */
+#define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_S 0
+#define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0)
+#define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_S 2
+#define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2)
+#define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_S 4
+#define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4)
+#define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_S 6
+#define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6)
+#define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_S 8
+#define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8)
+#define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_S 10
+#define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10)
+#define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_S 12
+#define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12)
+#define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_S 14
+#define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14)
+#define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_S 16
+#define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16)
+#define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_S 18
+#define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18)
+#define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_S 20
+#define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20)
+#define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_S 22
+#define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22)
+#define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_S 24
+#define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24)
+#define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_S 26
+#define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26)
+#define E830_DMA_AGENT_AT1 0x000BE26C /* Reset Source: PCIR */
+#define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_S 0
+#define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0)
+#define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_S 2
+#define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2)
+#define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_S 4
+#define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4)
+#define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_S 6
+#define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6)
+#define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_S 8
+#define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8)
+#define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_S 10
+#define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10)
+#define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_S 12
+#define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12)
+#define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_S 14
+#define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14)
+#define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_S 16
+#define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16)
+#define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_S 18
+#define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18)
+#define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_S 20
+#define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20)
+#define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_S 22
+#define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22)
+#define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_S 24
+#define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24)
+#define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_S 26
+#define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26)
+#define E830_GLPCI_CAPSUP_DOE_EN_S 1
+#define E830_GLPCI_CAPSUP_DOE_EN_M BIT(1)
+#define E830_GLPCI_CAPSUP_GEN5_EXT_EN_S 12
+#define E830_GLPCI_CAPSUP_GEN5_EXT_EN_M BIT(12)
+#define E830_GLPCI_CAPSUP_PTM_EN_S 13
+#define E830_GLPCI_CAPSUP_PTM_EN_M BIT(13)
+#define E830_GLPCI_CAPSUP_SNPS_RAS_EN_S 14
+#define E830_GLPCI_CAPSUP_SNPS_RAS_EN_M BIT(14)
+#define E830_GLPCI_CAPSUP_SIOV_EN_S 15
+#define E830_GLPCI_CAPSUP_SIOV_EN_M BIT(15)
+#define E830_GLPCI_CAPSUP_PTM_VSEC_EN_S 22
+#define E830_GLPCI_CAPSUP_PTM_VSEC_EN_M BIT(22)
+#define E830_GLPCI_CAPSUP_SNPS_RAS_PROT_EN_S 23
+#define E830_GLPCI_CAPSUP_SNPS_RAS_PROT_EN_M BIT(23)
+#define E830_GLPCI_DOE_BUSY_STATUS 0x0009DF70 /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_S 0
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_M BIT(0)
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_S 1
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_M BIT(1)
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_S 2
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_M BIT(2)
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_S 3
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_M BIT(3)
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_S 4
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_M BIT(4)
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_S 5
+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_M BIT(5)
+#define E830_GLPCI_DOE_CFG 0x0009DF54 /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_CFG_ENABLE_S 0
+#define E830_GLPCI_DOE_CFG_ENABLE_M BIT(0)
+#define E830_GLPCI_DOE_CFG_ITR_SUPPORT_S 1
+#define E830_GLPCI_DOE_CFG_ITR_SUPPORT_M BIT(1)
+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_S 2
+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_M BIT(2)
+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_S 3
+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_M BIT(3)
+#define E830_GLPCI_DOE_CFG_MSIX_VECTOR_S 8
+#define E830_GLPCI_DOE_CFG_MSIX_VECTOR_M MAKEMASK(0x7FF, 8)
+#define E830_GLPCI_DOE_CTRL 0x0009DF60 /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_S 0
+#define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_M BIT(0)
+#define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_S 1
+#define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_M BIT(1)
+#define E830_GLPCI_DOE_DBG 0x0009DF6C /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_DBG_CFG_BUSY_S 0
+#define E830_GLPCI_DOE_DBG_CFG_BUSY_M BIT(0)
+#define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_S 1
+#define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_M BIT(1)
+#define E830_GLPCI_DOE_DBG_CFG_ERROR_S 2
+#define E830_GLPCI_DOE_DBG_CFG_ERROR_M BIT(2)
+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_S 3
+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_M BIT(3)
+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_S 4
+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_M BIT(4)
+#define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_S 8
+#define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_M MAKEMASK(0x1FF, 8)
+#define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_S 20
+#define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_M MAKEMASK(0x1FF, 20)
+#define E830_GLPCI_DOE_ERR_EN 0x0009DF64 /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_S 0
+#define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_M BIT(0)
+#define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_S 1
+#define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_M BIT(1)
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_S 2
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_M BIT(2)
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_S 3
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_M BIT(3)
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_S 4
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_M BIT(4)
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_S 5
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_M BIT(5)
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_S 6
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_M BIT(6)
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_S 7
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_M BIT(7)
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_S 8
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_M BIT(8)
+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_S 9
+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_M BIT(9)
+#define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_S 10
+#define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_M BIT(10)
+#define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_S 11
+#define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_M BIT(11)
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_S 12
+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(12)
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_S 13
+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_M BIT(13)
+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_S 14
+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(14)
+#define E830_GLPCI_DOE_ERR_STATUS 0x0009DF68 /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_S 0
+#define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_M BIT(0)
+#define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_S 1
+#define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_M BIT(1)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_S 2
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_M BIT(2)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_S 3
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_M BIT(3)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_S 4
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_M BIT(4)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_S 5
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_M BIT(5)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_S 6
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_M BIT(6)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_S 7
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_M BIT(7)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_S 8
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_M BIT(8)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_S 9
+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_M BIT(9)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_S 10
+#define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_M BIT(10)
+#define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_S 11
+#define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_M BIT(11)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_S 12
+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_M BIT(12)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_S 13
+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_M BIT(13)
+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_S 14
+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_M BIT(14)
+#define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_S 24
+#define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_M MAKEMASK(0x1F, 24)
+#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS 0x0009DF58 /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_S 0
+#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0)
+#define E830_GLPCI_DOE_RESP 0x0009DF5C /* Reset Source: PCIR */
+#define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_S 0
+#define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0)
+#define E830_GLPCI_DOE_RESP_READY_SET_S 16
+#define E830_GLPCI_DOE_RESP_READY_SET_M BIT(16)
+#define E830_GLPCI_ERR_DBG 0x0009DF84 /* Reset Source: PCIR */
+#define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_S 0
+#define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_M MAKEMASK(0x3, 0)
+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_S 2
+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_M BIT(2)
+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_S 3
+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_M MAKEMASK(0x7, 3)
+#define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_S 6
+#define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_M MAKEMASK(0xF, 6)
+#define E830_GLPCI_NPQ_CFG_HIGH_TO_S 20
+#define E830_GLPCI_NPQ_CFG_HIGH_TO_M BIT(20)
+#define E830_GLPCI_NPQ_CFG_INC_150MS_TO_S 21
+#define E830_GLPCI_NPQ_CFG_INC_150MS_TO_M BIT(21)
+#define E830_GLPCI_PUSH_PQM_CTRL 0x0009DF74 /* Reset Source: POR */
+#define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_S 0
+#define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_M BIT(0)
+#define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_S 1
+#define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_M BIT(1)
+#define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_S 2
+#define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_M BIT(2)
+#define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_S 3
+#define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_M BIT(3)
+#define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_S 4
+#define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_M BIT(4)
+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_S 8
+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_M MAKEMASK(0xF, 8)
+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_S 12
+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_M BIT(12)
+#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_S 16
+#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_M BIT(16)
+#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_1DW_ON_XLR_S 17
+#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_1DW_ON_XLR_M BIT(17)
+#define E830_GLPCI_PUSH_PQM_DBG 0x0009DF7C /* Reset Source: PCIR */
+#define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_S 0
+#define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_M MAKEMASK(0xFF, 0)
+#define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_S 8
+#define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_M MAKEMASK(0xFF, 8)
+#define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_S 16
+#define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_M MAKEMASK(0xF, 16)
+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_S 20
+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_M MAKEMASK(0x1F, 20)
+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_S 25
+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_M BIT(25)
+#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS 0x0009DF78 /* Reset Source: PCIR */
+#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_S 0
+#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_M BIT(0)
+#define E830_GLPCI_RDPU_CMD_DBG 0x000BE264 /* Reset Source: PCIR */
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_S 0
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_M MAKEMASK(0xFF, 0)
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_S 8
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_M MAKEMASK(0xFF, 8)
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_S 16
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_M MAKEMASK(0xFF, 16)
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_S 24
+#define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_M MAKEMASK(0xFF, 24)
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0 0x000BE25C /* Reset Source: PCIR */
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_S 0
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0)
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_S 16
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16)
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1 0x000BE260 /* Reset Source: PCIR */
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_S 0
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0)
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_S 16
+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16)
+#define E830_GLPCI_RDPU_TAG 0x000BE258 /* Reset Source: PCIR */
+#define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_S 0
+#define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_M MAKEMASK(0xFF, 0)
+#define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_S 8
+#define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_M MAKEMASK(0x3FF, 8)
+#define E830_GLPCI_SB_AER_MSG_OUT 0x0009DF80 /* Reset Source: PCIR */
+#define E830_GLPCI_SB_AER_MSG_OUT_EN_S 0
+#define E830_GLPCI_SB_AER_MSG_OUT_EN_M BIT(0)
+#define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_S 1
+#define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_M BIT(1)
+#define E830_PF_FUNC_RID_HOST_S 16
+#define E830_PF_FUNC_RID_HOST_M MAKEMASK(0x3, 16)
+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI(_i) (0x00553004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_MAX_INDEX 127
+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_S 0
+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_M MAKEMASK(0xFFFFFF, 0)
+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO(_i) (0x00553000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_MAX_INDEX 127
+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S 0
+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPES_PFRXRPCNPHANDLED(_i) (0x00552C00 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define E830_GLPES_PFRXRPCNPHANDLED_MAX_INDEX 127
+#define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_S 0
+#define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPES_PFRXRPCNPIGNORED(_i) (0x00552800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define E830_GLPES_PFRXRPCNPIGNORED_MAX_INDEX 127
+#define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_S 0
+#define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_M MAKEMASK(0xFFFFFF, 0)
+#define E830_GLPES_PFTXNPCNPSENT(_i) (0x00553800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
+#define E830_GLPES_PFTXNPCNPSENT_MAX_INDEX 127
+#define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_S 0
+#define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_M MAKEMASK(0xFFFFFF, 0)
+#define E830_GLQF_FLAT_HLUT(_i) (0x004C0000 + ((_i) * 4)) /* _i=0...8191 */ /* Reset Source: CORER */
+#define E830_GLQF_FLAT_HLUT_MAX_INDEX 8191
+#define E830_GLQF_FLAT_HLUT_LUT0_S 0
+#define E830_GLQF_FLAT_HLUT_LUT0_M MAKEMASK(0xFF, 0)
+#define E830_GLQF_FLAT_HLUT_LUT1_S 8
+#define E830_GLQF_FLAT_HLUT_LUT1_M MAKEMASK(0xFF, 8)
+#define E830_GLQF_FLAT_HLUT_LUT2_S 16
+#define E830_GLQF_FLAT_HLUT_LUT2_M MAKEMASK(0xFF, 16)
+#define E830_GLQF_FLAT_HLUT_LUT3_S 24
+#define E830_GLQF_FLAT_HLUT_LUT3_M MAKEMASK(0xFF, 24)
+#define E830_GLQF_QGRP_CNTX(_i) (0x00490000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
+#define E830_GLQF_QGRP_CNTX_MAX_INDEX 2047
+#define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_S 0
+#define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_M MAKEMASK(0x7FFF, 0)
+#define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_S 16
+#define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_M MAKEMASK(0xF, 16)
+#define E830_GLQF_QGRP_CNTX_VSI_S 20
+#define E830_GLQF_QGRP_CNTX_VSI_M MAKEMASK(0x3FF, 20)
+#define E830_GLQF_QGRP_PF_OWNER(_i) (0x00484000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
+#define E830_GLQF_QGRP_PF_OWNER_MAX_INDEX 2047
+#define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_S 0
+#define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_M MAKEMASK(0x7, 0)
+#define E830_PFQF_LUT_ALLOC 0x0048E000 /* Reset Source: CORER */
+#define E830_PFQF_LUT_ALLOC_LUT_BASE_S 0
+#define E830_PFQF_LUT_ALLOC_LUT_BASE_M MAKEMASK(0x7FFF, 0)
+#define E830_PFQF_LUT_ALLOC_LUT_SIZE_S 16
+#define E830_PFQF_LUT_ALLOC_LUT_SIZE_M MAKEMASK(0xF, 16)
+#define E830_VSIQF_DEF_QGRP(_VSI) (0x00486000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define E830_VSIQF_DEF_QGRP_MAX_INDEX 767
+#define E830_VSIQF_DEF_QGRP_DEF_QGRP_S 0
+#define E830_VSIQF_DEF_QGRP_DEF_QGRP_M MAKEMASK(0x7FF, 0)
+#define E830_GLPRT_BPRCH_BPRCH_S 0
+#define E830_GLPRT_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
+#define E830_GLPRT_BPRCL_BPRCL_S 0
+#define E830_GLPRT_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPRT_BPTCH_BPTCH_S 0
+#define E830_GLPRT_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
+#define E830_GLPRT_BPTCL_BPTCL_S 0
+#define E830_GLPRT_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPRT_UPTCL_UPTCL_S 0
+#define E830_GLPRT_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPTM_ART_CTL 0x00088B50 /* Reset Source: POR */
+#define E830_GLPTM_ART_CTL_ACTIVE_S 0
+#define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0)
+#define E830_GLPTM_ART_CTL_TIME_OUT_S 1
+#define E830_GLPTM_ART_CTL_TIME_OUT_M BIT(1)
+#define E830_GLPTM_ART_CTL_PTM_READY_S 2
+#define E830_GLPTM_ART_CTL_PTM_READY_M BIT(2)
+#define E830_GLPTM_ART_CTL_PTM_AUTO_S 3
+#define E830_GLPTM_ART_CTL_PTM_AUTO_M BIT(3)
+#define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_S 4
+#define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_M BIT(4)
+#define E830_GLPTM_ART_CTL_LATCH_PTP_T1_S 5
+#define E830_GLPTM_ART_CTL_LATCH_PTP_T1_M BIT(5)
+#define E830_GLPTM_ART_CTL_AUTO_POURSE_S 6
+#define E830_GLPTM_ART_CTL_AUTO_POURSE_M BIT(6)
+#define E830_GLPTM_ART_TIME_H 0x00088B54 /* Reset Source: POR */
+#define E830_GLPTM_ART_TIME_H_ART_TIME_H_S 0
+#define E830_GLPTM_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLPTM_ART_TIME_L 0x00088B58 /* Reset Source: POR */
+#define E830_GLPTM_ART_TIME_L_ART_TIME_L_S 0
+#define E830_GLPTM_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_PTMTIME_H(_i) (0x00088B48 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GLTSYN_PTMTIME_H_MAX_INDEX 1
+#define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_S 0
+#define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_PTMTIME_L(_i) (0x00088B40 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
+#define E830_GLTSYN_PTMTIME_L_MAX_INDEX 1
+#define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_S 0
+#define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_H_0_AL 0x0008A004 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_H_1_AL 0x0008B004 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_L_0_AL 0x0008A000 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_L_1_AL 0x0008B000 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_PFPTM_SEM 0x00088B00 /* Reset Source: PFR */
+#define E830_PFPTM_SEM_BUSY_S 0
+#define E830_PFPTM_SEM_BUSY_M BIT(0)
+#define E830_PFPTM_SEM_PF_OWNER_S 4
+#define E830_PFPTM_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
+#define E830_VSI_PASID_1(_VSI) (0x00094000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define E830_VSI_PASID_1_MAX_INDEX 767
+#define E830_VSI_PASID_1_PASID_S 0
+#define E830_VSI_PASID_1_PASID_M MAKEMASK(0xFFFFF, 0)
+#define E830_VSI_PASID_1_EN_S 31
+#define E830_VSI_PASID_1_EN_M BIT(31)
+#define E830_VSI_PASID_2(_VSI) (0x00095000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define E830_VSI_PASID_2_MAX_INDEX 767
+#define E830_VSI_PASID_2_PASID_S 0
+#define E830_VSI_PASID_2_PASID_M MAKEMASK(0xFFFFF, 0)
+#define E830_VSI_PASID_2_EN_S 31
+#define E830_VSI_PASID_2_EN_M BIT(31)
+#define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_S 15
+#define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_M MAKEMASK(0x3F, 15)
+#define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_S 29
+#define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_M MAKEMASK(0x3, 29)
+#define E830_VFPE_MRTEIDXMASK_MAX_INDEX 255
+#define E830_VSIQF_QGRP_CFG(_VSI) (0x00492000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
+#define E830_VSIQF_QGRP_CFG_MAX_INDEX 767
+#define E830_VSIQF_QGRP_CFG_VSI_QGRP_ENABLE_S 0
+#define E830_VSIQF_QGRP_CFG_VSI_QGRP_ENABLE_M BIT(0)
+#define E830_VSIQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_S 1
+#define E830_VSIQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_M MAKEMASK(0x7, 1)
+#define E830_GLDCB_RTC_BLOCKED 0x0012274C /* Reset Source: CORER */
+#define E830_GLDCB_RTC_BLOCKED_BLOCKED_S 0
+#define E830_GLDCB_RTC_BLOCKED_BLOCKED_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLDCB_RTCID 0x00122900 /* Reset Source: CORER */
+#define E830_GLDCB_RTCID_IMM_DROP_TC_S 0
+#define E830_GLDCB_RTCID_IMM_DROP_TC_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLDCB_RTCTI_CDS_SET 0x00122748 /* Reset Source: CORER */
+#define E830_GLDCB_RTCTI_CDS_SET_CDS_SET_S 0
+#define E830_GLDCB_RTCTI_CDS_SET_CDS_SET_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLDCB_RTCTQ_PD(_i) (0x00122700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GLDCB_RTCTQ_PD_MAX_INDEX 7
+#define E830_GLDCB_RTCTQ_PD_RXQNUM_S 0
+#define E830_GLDCB_RTCTQ_PD_RXQNUM_M MAKEMASK(0x7FF, 0)
+#define E830_GLDCB_RTCTQ_PD_IS_PF_Q_S 16
+#define E830_GLDCB_RTCTQ_PD_IS_PF_Q_M BIT(16)
+#define E830_GLDCB_RTCTQ_SET 0x00122750 /* Reset Source: CORER */
+#define E830_GLDCB_RTCTQ_SET_RTCTQ_VALID_S 0
+#define E830_GLDCB_RTCTQ_SET_RTCTQ_VALID_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLDCB_RTCTQ_STICKY_EN 0x00122754 /* Reset Source: CORER */
+#define E830_GLDCB_RTCTQ_STICKY_EN_EN_S 0
+#define E830_GLDCB_RTCTQ_STICKY_EN_EN_M BIT(0)
+#define E830_GLDCB_RTCTS_PD(_i) (0x00122720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
+#define E830_GLDCB_RTCTS_PD_MAX_INDEX 7
+#define E830_GLDCB_RTCTS_PD_PFCTIMER_S 0
+#define E830_GLDCB_RTCTS_PD_PFCTIMER_M MAKEMASK(0x3FFF, 0)
+#define E830_GLRPB_TC_TOTAL_PC(_i) (0x000ACD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
+#define E830_GLRPB_TC_TOTAL_PC_MAX_INDEX 31
+#define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_S 0
+#define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_VFINT_ITRN_64(_i, _j) (0x00002C00 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...2 */ /* Reset Source: CORER */
+#define E830_VFINT_ITRN_64_MAX_INDEX 63
+#define E830_VFINT_ITRN_64_INTERVAL_S 0
+#define E830_VFINT_ITRN_64_INTERVAL_M MAKEMASK(0xFFF, 0)
+#define E830_GLQTX_TXTIME_DBELL_LSB1(_DBQM) (0x0000D000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_DBELL_LSB1_MAX_INDEX 255
+#define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLQTX_TXTIME_DBELL_MSB1(_DBQM) (0x0000D004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_DBELL_MSB1_MAX_INDEX 255
+#define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB(_DBQM) (0x00040000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_MAX_INDEX 255
+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB(_DBQM) (0x00040004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_MAX_INDEX 255
+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_S 0
+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_H_0_AL1 0x00003004 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_H_1_AL1 0x0000300C /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_L_0_AL1 0x00003000 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_GLTSYN_TIME_L_1_AL1 0x00003008 /* Reset Source: CORER */
+#define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_S 0
+#define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
+#define E830_VSI_VSI2F_LEM(_VSI) (0x006100A0 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
+#define E830_VSI_VSI2F_LEM_MAX_INDEX 767
+#define E830_VSI_VSI2F_LEM_VFVMNUMBER_S 0
+#define E830_VSI_VSI2F_LEM_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
+#define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_S 10
+#define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
+#define E830_VSI_VSI2F_LEM_PFNUMBER_S 12
+#define E830_VSI_VSI2F_LEM_PFNUMBER_M MAKEMASK(0x7, 12)
+#define E830_VSI_VSI2F_LEM_BUFFERNUMBER_S 16
+#define E830_VSI_VSI2F_LEM_BUFFERNUMBER_M MAKEMASK(0x7, 16)
+#define E830_VSI_VSI2F_LEM_VSI_NUMBER_S 20
+#define E830_VSI_VSI2F_LEM_VSI_NUMBER_M MAKEMASK(0x3FF, 20)
+#define E830_VSI_VSI2F_LEM_VSI_ENABLE_S 31
+#define E830_VSI_VSI2F_LEM_VSI_ENABLE_M BIT(31)
#endif /* !_ICE_HW_AUTOGEN_H_ */
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index b0d238f7e0..35da0c8b9c 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -1359,13 +1359,16 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
return status;
/* Reject requests to write to read-only registers */
- switch (cmd->offset) {
- case GL_HICR_EN:
- case GLGEN_RSTAT:
+ if (hw->mac_type == ICE_MAC_E830) {
+ if (cmd->offset == E830_GL_HICR_EN)
+ return ICE_ERR_OUT_OF_RANGE;
+ } else {
+ if (cmd->offset == GL_HICR_EN)
+ return ICE_ERR_OUT_OF_RANGE;
+ }
+
+ if (cmd->offset == GLGEN_RSTAT)
return ICE_ERR_OUT_OF_RANGE;
- default:
- break;
- }
ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
cmd->offset, data->regval);
--
2.43.0
next prev parent reply other threads:[~2024-06-25 11:26 UTC|newest]
Thread overview: 428+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 15:40 [RFC] net/ice: Update base code with latest snapshot Ian Stokes
2024-05-01 8:19 ` Thomas Monjalon
2024-05-01 9:06 ` Bruce Richardson
2024-05-01 12:08 ` Thomas Monjalon
2024-06-12 14:59 ` [PATCH v2 000/148] Update net/ice base driver to latest upstream snapshot Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 001/148] net/ice/base: convert enum ice_status to int Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 002/148] net/ice/base: replace ICE_SUCCESS with int Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 003/148] net/ice/base: update E830 headers Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 004/148] net/ice/base: update phy config during link restart Anatoly Burakov
2024-06-19 14:42 ` Bruce Richardson
2024-06-12 14:59 ` [PATCH v2 005/148] net/ice/base: fix for pointer to variable outside scope Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 006/148] net/ice/base: add missing include for flow Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 007/148] net/ice/base: add ability to set markid via switch filter Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 008/148] net/ice/base: improve ice_debug_cq messages Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 009/148] net/ice/base: add mgmt netlist auth support command Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 010/148] net/ice/base: fix undefined variables Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 011/148] net/ice/base: fix get media type Anatoly Burakov
2024-06-19 14:53 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 012/148] net/ice/base: clean up __ice_aq_get_set_rss_lut() Anatoly Burakov
2024-06-13 6:17 ` Przemek Kitszel
2024-06-21 12:31 ` Burakov, Anatoly
2024-06-19 14:55 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 013/148] net/ice/base: update flow seg fields to declared bitmaps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 014/148] net/ice/base: update interface in ice_parse_common_caps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 015/148] net/ice/base: refactor (non) bitmap declarations Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 016/148] net/ice/base: remove unnecessary control queue cmd_buf arrays Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 017/148] net/ice/base: alloc port_info only once Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 018/148] net/ice/base: update code with flex array safe allocations Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 019/148] net/ice/base: bring back ability to use 128 as size of PF type RSS LUT Anatoly Burakov
2024-06-19 15:51 ` Przemek Kitszel
2024-06-12 15:00 ` [PATCH v2 020/148] net/ice/base: support for OROM update in recovery mode Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 021/148] net/ice/base: code adjustments for E830 Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 022/148] net/ice/base: improve find recipe routine Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 023/148] net/ice/base: fix memory leak when checking firmware version Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 024/148] net/ice/base: add LL Tx timestamp interrupt read Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 025/148] net/ice/base: use model-dependent number of PHY ports Anatoly Burakov
2024-06-19 15:32 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 026/148] net/ice/base: use ice_bitmap_t in promisc functions Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 027/148] net/ice/base: fix rx-only unicast promiscuous mode Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 028/148] net/ice/base: add support for E825-C TX clock changing Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 029/148] net/ice/base: fix for applying multiple cloud filters Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 030/148] net/ice/base: limit PF RSS LUT to one VSI at time Anatoly Burakov
2024-06-19 15:41 ` Bruce Richardson
2024-06-19 15:53 ` Przemek Kitszel
2024-06-12 15:00 ` [PATCH v2 031/148] net/ice/base: prevent potential integer overflow Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 032/148] net/ice/base: cosmetic changes Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 033/148] net/ice/base: implement initial PTP support for E830 Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 034/148] net/ice/base: fix resource leak Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 035/148] net/ice/base: move lock outside of if-else Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 036/148] net/ice/base: refactor control queue send delay Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 037/148] net/ice/base: fix NVM feature check Anatoly Burakov
2024-06-20 10:28 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 038/148] net/ice/base: allow for dumping all clusters Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 039/148] net/ice/base: remove PTP aqc_driver_params Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 040/148] net/ice/base: add FW load status mask Anatoly Burakov
2024-06-20 10:29 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 041/148] net/ice/base: add direction metadata Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 042/148] net/ice/base: change data buffer in i2c write to be const Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 043/148] net/ice/base: remove unused code from upstream build Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 044/148] net/ice/base: fix sign-extension Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 045/148] net/ice/base: implement switch recipe reuse feature Anatoly Burakov
2024-06-18 14:53 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 046/148] net/ice/base: add helper function for refsync Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 047/148] net/ice/base: added informational message for NAC topology Anatoly Burakov
2024-06-20 12:02 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 048/148] net/ice/base: add Cage Max Power override NVM module Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 049/148] net/ice/base: adapt No FEC in Auto support check to add E82X devices Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 050/148] net/ice/base: move (read|write)_sma_ctrl functions to match upstream Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 051/148] net/ice/base: fix incorrect size when allocating children arrays Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 052/148] net/ice/base: fix GCS descriptor field offsets Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 053/148] net/ice/base: add VSI type for subfunctions Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 054/148] net/ice/base: correct the return type of ice_bitmap_hweight Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 055/148] net/ice/base: fix ice_ptp_one_port_cmd to avoid stale PHY commands Anatoly Burakov
2024-06-18 15:10 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 056/148] net/ice/base: remove dead code from ice_get_ddp_pkg_state Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 057/148] net/ice/base: get rid of enum ice_status Anatoly Burakov
2024-06-18 15:19 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 058/148] net/ice/base: use ICE_PTP_NOP to better indicate no action Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 059/148] net/ice/base: add fw log file Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 060/148] net/ice/base: update comments regarding clearing timestamps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 061/148] net/ice/base: use "err" instead of "status" in ice_ptp_hw.c Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 062/148] net/ice/base: re-number E810-T subdevice IDs to match upstream Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 063/148] net/ice/base: enable RDMA Act-Act unload paths Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 064/148] net/ice/base: parse 1PPS GPIO in 1588 function caps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 065/148] net/ice/base: rename netlist check functions to match upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 066/148] net/ice/base: fix check for existing switch rule Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 067/148] net/ice/base: fall back to safe CGU params Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 068/148] net/ice/base: change tmr_idx to u32 Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 069/148] net/ice/base: be more verbose when preparing timer sync Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 070/148] net/ice/base: be more verbose in configuring Rx timestamp offset Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 071/148] net/ice/base: match code style to upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 072/148] net/ice/base: update strict status when assigning BW limits Anatoly Burakov
2024-06-20 13:32 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 073/148] net/ice/base: remove unused define Anatoly Burakov
2024-06-20 13:38 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 074/148] net/ice/base: improve read retry value calculation Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 075/148] net/ice/base: check if recipe buffer was already allocated Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 076/148] net/ice/base: fix handling recipes when reusing is not supported Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 077/148] net/ice/base: use correct type Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 078/148] net/ice/base: read OROM in a loop Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 079/148] net/ice/base: ignore snprintf return value Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 080/148] net/ice/base: check array bounds Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 081/148] net/ice/base: copy output IO params from command descriptor Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 082/148] net/ice/base: enable Next Cluster ID capability Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 083/148] net/ice/base: fix potential TLV length overflow Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 084/148] net/ice/base: add function to read SDP section from NVM Anatoly Burakov
2024-06-20 14:44 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 085/148] net/ice/base: add Floating VEB support Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 086/148] net/ice/base: add defines for loopback mode Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 087/148] net/ice/base: allow skipping PF clear Anatoly Burakov
2024-06-20 14:56 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 088/148] net/ice/base: fix in the definition of the Board Type Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 089/148] net/ice/base : make ice_clear_vsi_q_ctx() non-static Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 090/148] net/ice/base: fix package download algorithm Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 091/148] net/ice/base: allows packages with mixed signature presence Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 092/148] net/ice/base: fix ice_memcpy type specifiers Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 093/148] net/ice/base: allow different FW API versions based on MAC type Anatoly Burakov
2024-06-20 15:41 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 094/148] net/ice/base: add 32 GT bus speed enumerated value Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 095/148] net/ice/base: add E830 debug dump cluster ID values Anatoly Burakov
2024-06-20 15:43 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 096/148] net/ice/base: fix for preparing PHY for timesync command Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 097/148] net/ice/base: support for firmware sanitization Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 098/148] net/ice/base: add 200G speeds to PHY types decoding Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 099/148] net/ice/base: temporary workaround for E830 signed package support Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 100/148] net/ice/base: add PHY OFFSET_READY register clearing Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 101/148] net/ice/base: rename PHY model designator fields and functions Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 102/148] net/ice/base: enable SB access explicitly before 1st PHY access Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 103/148] net/ice/base: refactor ETH56G PHY initialization Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 104/148] net/ice/base: refactor ETH56G support for miltiple PHYs per MAC Anatoly Burakov
2024-06-18 16:19 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 105/148] net/ice/base: implement interface to reset timestamp memory Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 106/148] net/ice/base: fix iterations over PTP ports Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 107/148] net/ice/base: return high address for multi-read eth56g registers Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 108/148] net/ice/base: add function to read Tx timestamp status register Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 109/148] net/ice/base: implement upper-level PHY control functions Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 110/148] net/ice/base: squash multiple fixes for e56g device Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 111/148] net/ice/base: add PHY statistics dump Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 112/148] net/ice/base: move ice_ptp_init_phy_model to align with upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 113/148] net/ice/base: add Get Link Status Data version 2 Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 114/148] net/ice/base: add port option commands Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 115/148] net/ice/base: merge unified E830 headers Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 116/148] net/ice/base: replace array initialization with macros Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 117/148] net/ice/base: switch speed conversions to static lookups Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 118/148] net/ice/base: support E830 in DDP pkg handling Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 119/148] net/ice/base: support E830 in Topology AQ command Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 120/148] net/ice/base: add E830 PTP init Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 121/148] net/ice/base: allow skipping main timer programming Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 122/148] net/ice/base: add missing files for shared code update Anatoly Burakov
2024-06-21 13:47 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 123/148] net/ice/base: align code to upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 124/148] net/ice/base: use const char* array for storing link modes Anatoly Burakov
2024-06-21 14:00 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 125/148] net/ice/base: fix compile issues on some targets Anatoly Burakov
2024-06-18 17:05 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 126/148] net/ice/base: move code to common headers Anatoly Burakov
2024-06-21 14:02 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 127/148] net/ice/base: make some switch-related functions static Anatoly Burakov
2024-06-21 14:03 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 128/148] net/ice/base: add support for L2TP on switch Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 129/148] net/ice/base: add L2TPv3 support for adv rules Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 130/148] net/ice/base: detect and store device sensor reading capability Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 131/148] net/ice/base: add missing defines and misc cleanup Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 132/148] net/ice/base: increase PF reset wait timeout to 500 milliseconds Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 133/148] net/ice/base: fix memcpy type Anatoly Burakov
2024-06-21 14:40 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 134/148] net/ice/base: too big a timeout for QV diagnostic tests Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 135/148] net/ice/base: fix ice_get_ctx() issue Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 136/148] net/ice/base: add AQ function to configure SyncE error reporting Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 137/148] net/ice/base: support DCF query port ETS adminq Anatoly Burakov
2024-06-21 14:49 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 138/148] net/ice/base: update boost struct for traffic types Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 139/148] net/ice/base: clean up ice_lan_tx_rx Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 140/148] net/ice/base: enable CGU error reporting Anatoly Burakov
2024-06-21 15:08 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 141/148] net/ice/base: cleanup timestamp registers correctly Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 142/148] net/ice/base: rework multiple functions Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 143/148] net/ice/base: change a method to get pca9575 handle Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 144/148] net/ice/base: rename SMA register macros to match Linux upstream Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 145/148] net/ice/base: introduce new functions in ice_sched_node Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 146/148] net/ice/base: misc header file clean up Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 147/148] net/ice: update rss lut value for RSS init Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 148/148] net/ice: add new device ids Anatoly Burakov
2024-06-12 15:08 ` [PATCH v2 000/148] Update net/ice base driver to latest upstream snapshot Burakov, Anatoly
2024-06-12 15:51 ` Ferruh Yigit
2024-06-12 18:29 ` Burakov, Anatoly
2024-06-25 11:12 ` [PATCH v3 000/129] " Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 001/129] net/ice/base: convert enum ice_status to int Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 002/129] net/ice/base: replace ICE_SUCCESS with int Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 003/129] net/ice/base: add E830 definitions Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 004/129] net/ice/base: update phy config during link restart Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 005/129] net/ice/base: fix for pointer to variable outside scope Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 006/129] net/ice/base: add missing include Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 007/129] net/ice/base: add ability to set markid via switch filter Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 008/129] net/ice/base: improve ice_debug_cq messages Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 009/129] net/ice/base: add mgmt netlist auth support command Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 010/129] net/ice/base: avoid undefined variables Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 011/129] net/ice/base: improve media type handling for phy caps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 012/129] net/ice/base: update flow seg fields to declared bitmaps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 013/129] net/ice/base: update interface in ice_parse_common_caps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 014/129] net/ice/base: refactor (non) bitmap declarations Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 015/129] net/ice/base: remove unnecessary control queue cmd_buf arrays Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 016/129] net/ice/base: alloc port_info only once Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 017/129] net/ice/base: update code with flex array safe allocations Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 018/129] net/ice/base: support for OROM update in recovery mode Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 019/129] net/ice/base: improve find recipe routine Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 020/129] net/ice/base: fix memory leak when checking firmware version Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 021/129] net/ice/base: add LL Tx timestamp interrupt read Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 022/129] net/ice/base: use model-dependent number of PHY ports Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 023/129] net/ice/base: use ice_bitmap_t in promisc functions Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 024/129] net/ice/base: fix rx-only unicast promiscuous mode Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 025/129] net/ice/base: add support for E825-C TX clock changing Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 026/129] net/ice/base: fix for applying multiple cloud filters Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 027/129] net/ice/base: prevent potential integer overflow Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 028/129] net/ice/base: implement initial PTP support for E830 Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 029/129] net/ice/base: fix resource leak Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 030/129] net/ice/base: move lock outside of if-else Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 031/129] net/ice/base: refactor control queue send delay Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 032/129] net/ice/base: allow for dumping all clusters Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 033/129] net/ice/base: remove PTP aqc_driver_params Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 034/129] net/ice/base: change data buffer in i2c write to be const Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 035/129] net/ice/base: fix sign-extension Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 036/129] net/ice/base: add helper function for refsync Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 037/129] net/ice/base: added informational message for NAC topology Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 038/129] net/ice/base: add Cage Max Power override NVM module Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 039/129] net/ice/base: adapt No FEC in Auto support check to add E82X devices Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 040/129] net/ice/base: fix incorrect size when allocating children arrays Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 041/129] net/ice/base: fix GCS descriptor field offsets Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 042/129] net/ice/base: add VSI type for subfunctions Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 043/129] net/ice/base: correct the return type of ice_bitmap_hweight Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 044/129] net/ice/base: fix ice_ptp_one_port_cmd to avoid stale PHY commands Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 045/129] net/ice/base: remove dead code from ice_get_ddp_pkg_state Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 046/129] net/ice/base: use ICE_PTP_NOP to better indicate no action Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 047/129] net/ice/base: add fw log file Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 048/129] net/ice/base: use "err" instead of "status" in ice_ptp_hw.c Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 049/129] net/ice/base: re-number E810-T subdevice IDs to match upstream Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 050/129] net/ice/base: enable RDMA Act-Act unload paths Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 051/129] net/ice/base: parse 1PPS GPIO in 1588 function caps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 052/129] net/ice/base: fix check for existing switch rule Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 053/129] net/ice/base: fall back to safe CGU params Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 054/129] net/ice/base: change tmr_idx to u32 Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 055/129] net/ice/base: be more verbose when preparing timer sync Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 056/129] net/ice/base: update strict status when assigning BW limits Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 057/129] net/ice/base: improve read retry value calculation Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 058/129] net/ice/base: check if recipe buffer was already allocated Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 059/129] net/ice/base: use correct type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 060/129] net/ice/base: read OROM in a loop Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 061/129] net/ice/base: ignore snprintf return value Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 062/129] net/ice/base: check array bounds Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 063/129] net/ice/base: copy output IO params from command descriptor Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 064/129] net/ice/base: enable Next Cluster ID capability Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 065/129] net/ice/base: fix potential TLV length overflow Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 066/129] net/ice/base: add function to read SDP section from NVM Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 067/129] net/ice/base: add Floating VEB support Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 068/129] net/ice/base: add defines for loopback mode Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 069/129] net/ice/base: allow skipping PF clear Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 070/129] net/ice/base: fix in the definition of the Board Type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 071/129] net/ice/base: make ice_clear_vsi_q_ctx() non-static Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 072/129] net/ice/base: fix package download algorithm Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 073/129] net/ice/base: allows packages with mixed signature presence Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 074/129] net/ice/base: fix ice_memcpy type specifiers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 075/129] net/ice/base: allow different FW API versions based on MAC type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 076/129] net/ice/base: add 32 GT bus speed enumerated value Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 077/129] net/ice/base: add E830 debug dump cluster ID values Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 078/129] net/ice/base: fix for preparing PHY for timesync command Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 079/129] net/ice/base: support for firmware sanitization Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 080/129] net/ice/base: add 200G speeds to PHY types decoding Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 081/129] net/ice/base: add PHY OFFSET_READY register clearing Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 082/129] net/ice/base: rename PHY model designator fields and functions Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 083/129] net/ice/base: enable SB access explicitly before 1st PHY access Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 084/129] net/ice/base: refactor ETH56G PHY initialization Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 085/129] net/ice/base: refactor ETH56G support for multiple PHYs per MAC Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 086/129] net/ice/base: implement interface to reset timestamp memory Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 087/129] net/ice/base: return high address for multi-read eth56g registers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 088/129] net/ice/base: add function to read Tx timestamp status register Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 089/129] net/ice/base: implement upper-level PHY control functions Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 090/129] net/ice/base: squash multiple fixes for e56g device Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 091/129] net/ice/base: allow passing flags to sbq command Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 092/129] net/ice/base: move ice_ptp_init_phy_model to align with upstream Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 093/129] net/ice/base: add Get Link Status Data version 2 Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 094/129] net/ice/base: add port option commands Anatoly Burakov
2024-06-25 11:13 ` Anatoly Burakov [this message]
2024-06-25 11:13 ` [PATCH v3 096/129] net/ice/base: replace array initialization with macros Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 097/129] net/ice/base: switch speed conversions to static lookups Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 098/129] net/ice/base: support E830 in DDP pkg handling Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 099/129] net/ice/base: support E830 in Topology AQ command Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 100/129] net/ice/base: add E830 PTP init Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 101/129] net/ice/base: allow skipping main timer programming Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 102/129] net/ice/base: add missing files for shared code update Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 103/129] net/ice/base: rename netlist check functions to match upstream Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 104/129] net/ice/base: align code to base driver Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 105/129] net/ice/base: use const char* array for storing link modes Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 106/129] net/ice/base: fix compile issues on some targets Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 107/129] net/ice/base: move code to common headers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 108/129] net/ice/base: make some switch-related functions static Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 109/129] net/ice/base: add L2TPv3 support for adv rules Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 110/129] net/ice/base: detect and store device sensor reading capability Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 111/129] net/ice/base: add missing defines and misc cleanup Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 112/129] net/ice/base: increase PF reset wait timeout to 500 milliseconds Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 113/129] net/ice/base: adjust memcpy type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 114/129] net/ice/base: use a variable to store reset count Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 115/129] net/ice/base: fix ice_get_ctx() issue Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 116/129] net/ice/base: add AQ function to configure SyncE error reporting Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 117/129] net/ice/base: support DCF query port ETS adminq Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 118/129] net/ice/base: update boost struct for traffic types Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 119/129] net/ice/base: clean up ice_lan_tx_rx Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 120/129] net/ice/base: enable CGU error reporting Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 121/129] net/ice/base: cleanup timestamp registers correctly Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 122/129] net/ice/base: remove PHY port timer bypass mode Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 123/129] net/ice/base: implement TX interrupt enablement functions Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 124/129] net/ice/base: make Tx and Rx vernier offset calibration independent Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 125/129] net/ice/base: change a method to get pca9575 handle Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 126/129] net/ice/base: rename SMA register macros to match Linux upstream Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 127/129] net/ice/base: introduce new functions in ice_sched_node Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 128/129] net/ice/base: misc header file clean up Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 129/129] net/ice: add new device ids Anatoly Burakov
2024-06-25 17:20 ` [PATCH v3 000/129] Update net/ice base driver to latest upstream snapshot Bruce Richardson
2024-06-26 11:40 ` [PATCH v4 000/103] " Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 001/103] net/ice/base: add LL Tx timestamp interrupt read Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 002/103] net/ice/base: use model-dependent number of PHY ports Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 003/103] net/ice/base: use ice_bitmap_t in promisc functions Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 004/103] net/ice/base: fix rx-only unicast promiscuous mode Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 005/103] net/ice/base: add support for E825-C TX clock changing Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 006/103] net/ice/base: fix for applying multiple cloud filters Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 007/103] net/ice/base: prevent potential integer overflow Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 008/103] net/ice/base: implement initial PTP support for E830 Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 009/103] net/ice/base: fix resource leak Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 010/103] net/ice/base: move lock outside of if-else Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 011/103] net/ice/base: refactor control queue send delay Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 012/103] net/ice/base: allow for dumping all clusters Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 013/103] net/ice/base: remove PTP aqc_driver_params Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 014/103] net/ice/base: change data buffer in i2c write to be const Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 015/103] net/ice/base: fix sign-extension Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 016/103] net/ice/base: add helper function for refsync Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 017/103] net/ice/base: added informational message for NAC topology Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 018/103] net/ice/base: add Cage Max Power override NVM module Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 019/103] net/ice/base: adapt No FEC in Auto support check to add E82X devices Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 020/103] net/ice/base: fix incorrect size when allocating children arrays Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 021/103] net/ice/base: fix GCS descriptor field offsets Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 022/103] net/ice/base: add VSI type for subfunctions Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 023/103] net/ice/base: correct the return type of ice_bitmap_hweight Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 024/103] net/ice/base: add helper to get timer command reg values Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 025/103] net/ice/base: avoid stale PHY commands in ice_ptp_one_port_cmd Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 026/103] net/ice/base: remove dead code from ice_get_ddp_pkg_state Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 027/103] net/ice/base: use ICE_PTP_NOP to better indicate no action Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 028/103] net/ice/base: use "err" instead of "status" in ice_ptp_hw.c Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 029/103] net/ice/base: re-number E810-T subdevice IDs to match upstream Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 030/103] net/ice/base: enable RDMA Act-Act unload paths Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 031/103] net/ice/base: parse 1PPS GPIO in 1588 function caps Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 032/103] net/ice/base: fix check for existing switch rule Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 033/103] net/ice/base: fall back to safe CGU params Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 034/103] net/ice/base: change tmr_idx to u32 Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 035/103] net/ice/base: be more verbose when preparing timer sync Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 036/103] net/ice/base: update strict status when assigning BW limits Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 037/103] net/ice/base: improve read retry value calculation Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 038/103] net/ice/base: check if recipe buffer was already allocated Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 039/103] net/ice/base: use correct type Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 040/103] net/ice/base: read OROM in a loop Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 041/103] net/ice/base: ignore snprintf return value Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 042/103] net/ice/base: check array bounds Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 043/103] net/ice/base: copy output IO params from command descriptor Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 044/103] net/ice/base: enable Next Cluster ID capability Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 045/103] net/ice/base: fix potential TLV length overflow Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 046/103] net/ice/base: add function to read SDP section from NVM Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 047/103] net/ice/base: add Floating VEB support Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 048/103] net/ice/base: add defines for loopback mode Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 049/103] net/ice/base: allow skipping PF clear Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 050/103] net/ice/base: fix wrong definition of board type Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 051/103] net/ice/base: make ice_clear_vsi_q_ctx() non-static Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 052/103] net/ice/base: fix package download algorithm Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 053/103] net/ice/base: allows packages with mixed signature presence Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 054/103] net/ice/base: adjust ice_memcpy type specifiers Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 055/103] net/ice/base: allow different FW API versions based on MAC type Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 056/103] net/ice/base: add 32 GT bus speed enumerated value Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 057/103] net/ice/base: add E830 debug dump cluster ID values Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 058/103] net/ice/base: fix for preparing PHY for timesync command Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 059/103] net/ice/base: support for firmware sanitization Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 060/103] net/ice/base: add 200G speeds to PHY types decoding Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 061/103] net/ice/base: add PHY OFFSET_READY register clearing Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 062/103] net/ice/base: rename PHY model designator fields and functions Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 063/103] net/ice/base: enable SB access explicitly before 1st PHY access Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 064/103] net/ice/base: refactor ETH56G PHY initialization Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 065/103] net/ice/base: refactor ETH56G support for multiple PHYs per MAC Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 066/103] net/ice/base: implement interface to reset timestamp memory Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 067/103] net/ice/base: return high address for multi-read eth56g registers Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 068/103] net/ice/base: add function to read Tx timestamp status register Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 069/103] net/ice/base: implement upper-level PHY control functions Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 070/103] net/ice/base: remove switch-related code Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 071/103] net/ice/base: allow passing flags to sbq command Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 072/103] net/ice/base: add Get Link Status Data version 2 Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 073/103] net/ice/base: add port option commands Anatoly Burakov
2024-06-26 12:13 ` Burakov, Anatoly
2024-06-26 11:42 ` [PATCH v4 074/103] net/ice/base: replace array initialization with macros Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 075/103] net/ice/base: switch speed conversions to static lookups Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 076/103] net/ice/base: merge unified E830 headers Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 077/103] net/ice/base: support E830 in DDP pkg handling Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 078/103] net/ice/base: support E830 in Topology AQ command Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 079/103] net/ice/base: add E830 PTP init Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 080/103] net/ice/base: allow skipping main timer programming Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 081/103] net/ice/base: fix compile issues on some targets Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 082/103] net/ice/base: add L2TPv3 support for adv rules Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 083/103] net/ice/base: detect and store device sensor reading capability Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 084/103] net/ice/base: increase PF reset wait timeout to 500 milliseconds Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 085/103] net/ice/base: use a variable to store reset count Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 086/103] net/ice/base: fix masking in ice_get_ctx() Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 087/103] net/ice/base: add AQ function to configure SyncE error reporting Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 088/103] net/ice/base: update boost struct for traffic types Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 089/103] net/ice/base: enable CGU error reporting Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 090/103] net/ice/base: cleanup timestamp registers correctly Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 091/103] net/ice/base: remove PHY port timer bypass mode Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 092/103] net/ice/base: implement TX interrupt enablement functions Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 093/103] net/ice/base: make Tx and Rx vernier offset calibration independent Anatoly Burakov
2024-06-26 12:11 ` Burakov, Anatoly
2024-06-26 12:13 ` Bruce Richardson
2024-06-26 11:42 ` [PATCH v4 094/103] net/ice/base: change a method to get pca9575 handle Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 095/103] net/ice/base: rename SMA register macros Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 096/103] net/ice/base: make is_gps_present more generic Anatoly Burakov
2024-06-26 12:08 ` Burakov, Anatoly
2024-06-26 11:42 ` [PATCH v4 097/103] net/ice/base: add missing defines and misc cleanup Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 098/103] net/ice/base: align code to base driver Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 099/103] net/ice/base: make some functions non-static Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 100/103] net/ice/base: make some functions static Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 101/103] net/ice/base: introduce new functions in ice_sched_node Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 102/103] net/ice/base: add missing files for shared code update Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 103/103] net/ice: add new device ids Anatoly Burakov
2024-06-26 17:33 ` [PATCH v4 000/103] Update net/ice base driver to latest upstream snapshot Bruce Richardson
2024-06-27 17:43 ` Bruce Richardson
2024-06-28 11:23 ` Bruce Richardson
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