From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id C742A1BACA for ; Fri, 11 Jan 2019 20:07:53 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jan 2019 11:07:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,466,1539673200"; d="scan'208";a="266448834" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga004.jf.intel.com with ESMTP; 11 Jan 2019 11:07:52 -0800 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 11 Jan 2019 11:07:52 -0800 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.99]) by FMSMSX153.amr.corp.intel.com ([169.254.9.27]) with mapi id 14.03.0415.000; Fri, 11 Jan 2019 11:07:51 -0800 From: "Eads, Gage" To: Stephen Hemminger CC: "dev@dpdk.org" , "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" Thread-Topic: [dpdk-dev] [PATCH 1/6] ring: change head and tail to pointer-width size Thread-Index: AQHUqWeISGNAhgPQUEq3X66uBo4z+qWqa1aQ Date: Fri, 11 Jan 2019 19:07:50 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E541C4C2B@FMSMSX108.amr.corp.intel.com> References: <20190110210122.24889-1-gage.eads@intel.com> <20190110210122.24889-2-gage.eads@intel.com> <20190110203833.3e6a6ea2@hermes.lan> In-Reply-To: <20190110203833.3e6a6ea2@hermes.lan> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiY2FhMzE2NGUtZDkzMS00NjRhLTk3MjgtY2IzZTkzZDA1ODQ4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRlwvSDgxRW5Gb21NaGF5OEtCcmlVSmpSNTM2cmxrWUFUckNpMlhDdTllOHdDWFNTTG02NVNaTytTNUROZ3ZyeVEifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.1.200.108] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 1/6] ring: change head and tail to pointer-width size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Jan 2019 19:07:54 -0000 > -----Original Message----- > From: Stephen Hemminger [mailto:stephen@networkplumber.org] > Sent: Thursday, January 10, 2019 10:39 PM > To: Eads, Gage > Cc: dev@dpdk.org; olivier.matz@6wind.com; arybchenko@solarflare.com; > Richardson, Bruce ; Ananyev, Konstantin > > Subject: Re: [dpdk-dev] [PATCH 1/6] ring: change head and tail to pointer= -width > size >=20 > On Thu, 10 Jan 2019 15:01:17 -0600 > Gage Eads wrote: >=20 > > For 64-bit architectures, doubling the head and tail index widths > > greatly increases the time it takes for them to wrap-around (with > > current CPU speeds, it won't happen within the author's lifetime). > > This is important in avoiding the ABA problem -- in which a thread > > mistakes reading the same tail index in two accesses to mean that the > > ring was not modified in the intervening time -- in the upcoming > > non-blocking ring implementation. Using a 64-bit index makes the possib= ility of > this occurring effectively zero. > > > > I tested this commit's performance impact with an x86_64 build on a > > dual-socket Xeon E5-2699 v4 using ring_perf_autotest, and the change > > made no significant difference -- the few differences appear to be syst= em > noise. > > (The test ran on isolcpus cores using a tickless scheduler, but some > > variation was stll observed.) Each test was run three times and the > > results were averaged: > > > > | 64b head/tail cycle cost minus > > Test | 32b head/tail cycle cost > > ------------------------------------------------------------------ > > SP/SC single enq/dequeue | 0.33 > > MP/MC single enq/dequeue | 0.00 > > SP/SC burst enq/dequeue (size 8) | 0.00 MP/MC burst enq/dequeue (size > > 8) | 1.00 SP/SC burst enq/dequeue (size 32) | 0.00 MP/MC burst > > enq/dequeue (size 32) | -1.00 > > SC empty dequeue | 0.01 > > MC empty dequeue | 0.00 > > > > Single lcore: > > SP/SC bulk enq/dequeue (size 8) | -0.36 > > MP/MC bulk enq/dequeue (size 8) | 0.99 > > SP/SC bulk enq/dequeue (size 32) | -0.40 MP/MC bulk enq/dequeue (size > > 32) | -0.57 > > > > Two physical cores: > > SP/SC bulk enq/dequeue (size 8) | -0.49 > > MP/MC bulk enq/dequeue (size 8) | 0.19 > > SP/SC bulk enq/dequeue (size 32) | -0.28 MP/MC bulk enq/dequeue (size > > 32) | -0.62 > > > > Two NUMA nodes: > > SP/SC bulk enq/dequeue (size 8) | 3.25 > > MP/MC bulk enq/dequeue (size 8) | 1.87 > > SP/SC bulk enq/dequeue (size 32) | -0.44 MP/MC bulk enq/dequeue (size > > 32) | -1.10 > > > > An earlier version of this patch changed the head and tail indexes to > > uint64_t, but that caused a performance drop on 32-bit builds. With > > uintptr_t, no performance difference is observed on an i686 build. > > > > Signed-off-by: Gage Eads > > --- > > lib/librte_eventdev/rte_event_ring.h | 6 +++--- > > lib/librte_ring/rte_ring.c | 10 +++++----- > > lib/librte_ring/rte_ring.h | 20 ++++++++++---------- > > lib/librte_ring/rte_ring_generic.h | 16 +++++++++------- > > 4 files changed, 27 insertions(+), 25 deletions(-) > > > > diff --git a/lib/librte_eventdev/rte_event_ring.h > > b/lib/librte_eventdev/rte_event_ring.h > > index 827a3209e..eae70f904 100644 > > --- a/lib/librte_eventdev/rte_event_ring.h > > +++ b/lib/librte_eventdev/rte_event_ring.h > > @@ -1,5 +1,5 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > - * Copyright(c) 2016-2017 Intel Corporation > > + * Copyright(c) 2016-2019 Intel Corporation > > */ > > > > /** > > @@ -88,7 +88,7 @@ rte_event_ring_enqueue_burst(struct rte_event_ring *r= , > > const struct rte_event *events, > > unsigned int n, uint16_t *free_space) { > > - uint32_t prod_head, prod_next; > > + uintptr_t prod_head, prod_next; > > uint32_t free_entries; > > > > n =3D __rte_ring_move_prod_head(&r->r, r->r.prod.single, n, @@ -129,7 > > +129,7 @@ rte_event_ring_dequeue_burst(struct rte_event_ring *r, > > struct rte_event *events, > > unsigned int n, uint16_t *available) { > > - uint32_t cons_head, cons_next; > > + uintptr_t cons_head, cons_next; > > uint32_t entries; > > > > n =3D __rte_ring_move_cons_head(&r->r, r->r.cons.single, n, diff --gi= t > > a/lib/librte_ring/rte_ring.c b/lib/librte_ring/rte_ring.c index > > d215acecc..b15ee0eb3 100644 > > --- a/lib/librte_ring/rte_ring.c > > +++ b/lib/librte_ring/rte_ring.c > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * > > - * Copyright (c) 2010-2015 Intel Corporation > > + * Copyright (c) 2010-2019 Intel Corporation > > * Copyright (c) 2007,2008 Kip Macy kmacy@freebsd.org > > * All rights reserved. > > * Derived from FreeBSD's bufring.h > > @@ -227,10 +227,10 @@ rte_ring_dump(FILE *f, const struct rte_ring *r) > > fprintf(f, " flags=3D%x\n", r->flags); > > fprintf(f, " size=3D%"PRIu32"\n", r->size); > > fprintf(f, " capacity=3D%"PRIu32"\n", r->capacity); > > - fprintf(f, " ct=3D%"PRIu32"\n", r->cons.tail); > > - fprintf(f, " ch=3D%"PRIu32"\n", r->cons.head); > > - fprintf(f, " pt=3D%"PRIu32"\n", r->prod.tail); > > - fprintf(f, " ph=3D%"PRIu32"\n", r->prod.head); > > + fprintf(f, " ct=3D%"PRIuPTR"\n", r->cons.tail); > > + fprintf(f, " ch=3D%"PRIuPTR"\n", r->cons.head); > > + fprintf(f, " pt=3D%"PRIuPTR"\n", r->prod.tail); > > + fprintf(f, " ph=3D%"PRIuPTR"\n", r->prod.head); > > fprintf(f, " used=3D%u\n", rte_ring_count(r)); > > fprintf(f, " avail=3D%u\n", rte_ring_free_count(r)); } diff --git > > a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h index > > af5444a9f..12af64e13 100644 > > --- a/lib/librte_ring/rte_ring.h > > +++ b/lib/librte_ring/rte_ring.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * > > - * Copyright (c) 2010-2017 Intel Corporation > > + * Copyright (c) 2010-2019 Intel Corporation > > * Copyright (c) 2007-2009 Kip Macy kmacy@freebsd.org > > * All rights reserved. > > * Derived from FreeBSD's bufring.h > > @@ -65,8 +65,8 @@ struct rte_memzone; /* forward declaration, so as > > not to require memzone.h */ > > > > /* structure to hold a pair of head/tail values and other metadata */ > > struct rte_ring_headtail { > > - volatile uint32_t head; /**< Prod/consumer head. */ > > - volatile uint32_t tail; /**< Prod/consumer tail. */ > > + volatile uintptr_t head; /**< Prod/consumer head. */ > > + volatile uintptr_t tail; /**< Prod/consumer tail. */ > > uint32_t single; /**< True if single prod/cons */ > > }; >=20 > Isn't this a major ABI change which will break existing applications? Correct, and this patch needs to be reworked with the RTE_NEXT_ABI ifdef, a= s described in the versioning guidelines. I had misunderstood the ABI chang= e procedure, but I'll fix this in v2.